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Add another bit of the ARM target assembler to llvm-mc to parse registers

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with writeback, things like "sp!", etc.  Also added some more stuff to the
temporarily hacked methods ARMAsmParser::MatchRegisterName and
ARMAsmParser::MatchInstruction to allow more parser testing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83477 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kevin Enderby 2009-10-07 18:01:35 +00:00
parent 2627e08e05
commit 99e6d4e839
1 changed files with 17 additions and 3 deletions
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20
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@ -100,6 +100,7 @@ struct ARMOperand {
struct { struct {
unsigned RegNum; unsigned RegNum;
bool Writeback;
} Reg; } Reg;
// This is for all forms of ARM address expressions // This is for all forms of ARM address expressions
@ -146,10 +147,11 @@ struct ARMOperand {
return Res; return Res;
} }
static ARMOperand CreateReg(unsigned RegNum) { static ARMOperand CreateReg(unsigned RegNum, bool Writeback) {
ARMOperand Res; ARMOperand Res;
Res.Kind = Register; Res.Kind = Register;
Res.Reg.RegNum = RegNum; Res.Reg.RegNum = RegNum;
Res.Reg.Writeback = Writeback;
return Res; return Res;
} }
@ -193,10 +195,17 @@ bool ARMAsmParser::ParseRegister(ARMOperand &Op) {
RegNum = MatchRegisterName(Tok.getString()); RegNum = MatchRegisterName(Tok.getString());
if (RegNum == 0) if (RegNum == 0)
return true; return true;
Op = ARMOperand::CreateReg(RegNum);
getLexer().Lex(); // Eat identifier token. getLexer().Lex(); // Eat identifier token.
bool Writeback = false;
const AsmToken &ExclaimTok = getLexer().getTok();
if (ExclaimTok.is(AsmToken::Exclaim)) {
Writeback = true;
getLexer().Lex(); // Eat exclaim token
}
Op = ARMOperand::CreateReg(RegNum, Writeback);
return false; return false;
} }
@ -396,6 +405,8 @@ unsigned ARMAsmParser::MatchRegisterName(const StringRef &Name) {
return 2; return 2;
else if (Name == "r3") else if (Name == "r3")
return 3; return 3;
else if (Name == "sp")
return 13;
return 0; return 0;
} }
@ -406,6 +417,9 @@ bool ARMAsmParser::MatchInstruction(SmallVectorImpl<ARMOperand> &Operands,
assert(Op0.Kind == ARMOperand::Token && "First operand not a Token"); assert(Op0.Kind == ARMOperand::Token && "First operand not a Token");
const StringRef &Mnemonic = Op0.getToken(); const StringRef &Mnemonic = Op0.getToken();
if (Mnemonic == "add" || if (Mnemonic == "add" ||
Mnemonic == "stmfd" ||
Mnemonic == "str" ||
Mnemonic == "ldmfd" ||
Mnemonic == "ldr") Mnemonic == "ldr")
return false; return false;