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ARM LDR_PRE/LDR_POST/STR_PRE/STR_POST (and the *B counterparts) binary encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119180 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
bb6315d1e4
commit
99f53d13ef
@ -214,6 +214,10 @@ namespace {
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Binary |= (Reg << 13);
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return Binary;
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}
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uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx)
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const { return 0;}
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uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
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const { return 0;}
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uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
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const { return 0;}
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uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op) const
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@ -438,11 +438,13 @@ class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops,
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string asm, string cstr, list<dag> pattern>
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: I<oops, iops, AddrMode2, Size4Bytes, im, f, itin,
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opc, asm, cstr, pattern> {
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bits<4> Rt;
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let Inst{27-26} = 0b01;
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let Inst{24} = isPre; // P bit
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let Inst{22} = isByte; // B bit
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let Inst{21} = isPre; // W bit
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let Inst{20} = isLd; // L bit
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let Inst{15-12} = Rt;
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}
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class AXI2ldw<dag oops, dag iops, Format f, InstrItinClass itin,
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@ -440,6 +440,7 @@ def ldst_so_reg : Operand<i32>,
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//
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def addrmode2 : Operand<i32>,
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ComplexPattern<i32, 3, "SelectAddrMode2", []> {
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string EncoderMethod = "getAddrMode2OpValue";
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let PrintMethod = "printAddrMode2Operand";
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let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
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}
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@ -447,6 +448,7 @@ def addrmode2 : Operand<i32>,
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def am2offset : Operand<i32>,
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ComplexPattern<i32, 2, "SelectAddrMode2Offset",
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[], [SDNPWantRoot]> {
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string EncoderMethod = "getAddrMode2OffsetOpValue";
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let PrintMethod = "printAddrMode2OffsetOperand";
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let MIOperandInfo = (ops GPR, i32imm);
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}
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@ -1550,11 +1552,31 @@ def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
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multiclass AI2_ldridx<bit isByte, string opc, InstrItinClass itin> {
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def _PRE : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
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(ins addrmode2:$addr), IndexModePre, LdFrm, itin,
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opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
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opc, "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
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// {17-14} Rn
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// {13} 1 == Rm, 0 == imm12
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// {12} isAdd
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// {11-0} imm12/Rm
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bits<18> addr;
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let Inst{25} = addr{13};
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let Inst{23} = addr{12};
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let Inst{19-16} = addr{17-14};
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let Inst{11-0} = addr{11-0};
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}
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def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
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(ins GPR:$Rn, am2offset:$offset),
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IndexModePost, LdFrm, itin,
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opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>;
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opc, "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []> {
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// {13} 1 == Rm, 0 == imm12
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// {12} isAdd
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// {11-0} imm12/Rm
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bits<14> offset;
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bits<4> Rn;
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let Inst{25} = offset{13};
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let Inst{23} = offset{12};
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let Inst{19-16} = Rn;
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let Inst{11-0} = offset{11-0};
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}
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}
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defm LDR : AI2_ldridx<0, "ldr", IIC_iLoad_ru>;
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@ -1647,19 +1669,39 @@ def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
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"strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
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// Indexed stores
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def STR_PRE : AI2ldstidx<0, 0, 1, (outs GPR:$base_wb),
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(ins GPR:$src, GPR:$base, am2offset:$offset),
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def STR_PRE : AI2ldstidx<0, 0, 1, (outs GPR:$Rn_wb),
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(ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
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IndexModePre, StFrm, IIC_iStore_ru,
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"str", "\t$src, [$base, $offset]!", "$base = $base_wb",
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[(set GPR:$base_wb,
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(pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
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"str", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
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[(set GPR:$Rn_wb,
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(pre_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]> {
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// {13} 1 == Rm, 0 == imm12
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// {12} isAdd
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// {11-0} imm12/Rm
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bits<14> offset;
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bits<4> Rn;
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let Inst{25} = offset{13};
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let Inst{23} = offset{12};
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let Inst{19-16} = Rn;
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let Inst{11-0} = offset{11-0};
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}
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def STR_POST : AI2ldstidx<0, 0, 0, (outs GPR:$base_wb),
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(ins GPR:$src, GPR:$base,am2offset:$offset),
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def STR_POST : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
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(ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
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IndexModePost, StFrm, IIC_iStore_ru,
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"str", "\t$src, [$base], $offset", "$base = $base_wb",
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[(set GPR:$base_wb,
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(post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
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"str", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
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[(set GPR:$Rn_wb,
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(post_store GPR:$Rt, GPR:$Rn, am2offset:$offset))]> {
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// {13} 1 == Rm, 0 == imm12
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// {12} isAdd
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// {11-0} imm12/Rm
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bits<14> offset;
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bits<4> Rn;
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let Inst{25} = offset{13};
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let Inst{23} = offset{12};
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let Inst{19-16} = Rn;
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let Inst{11-0} = offset{11-0};
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}
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def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
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(ins GPR:$src, GPR:$base,am3offset:$offset),
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@ -1675,19 +1717,39 @@ def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
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[(set GPR:$base_wb, (post_truncsti16 GPR:$src,
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GPR:$base, am3offset:$offset))]>;
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def STRB_PRE : AI2ldstidx<0, 1, 1, (outs GPR:$base_wb),
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(ins GPR:$src, GPR:$base,am2offset:$offset),
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def STRB_PRE : AI2ldstidx<0, 1, 1, (outs GPR:$Rn_wb),
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(ins GPR:$Rt, GPR:$Rn,am2offset:$offset),
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IndexModePre, StFrm, IIC_iStore_bh_ru,
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"strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
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[(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
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GPR:$base, am2offset:$offset))]>;
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"strb", "\t$Rt, [$Rn, $offset]!", "$Rn = $Rn_wb",
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[(set GPR:$Rn_wb, (pre_truncsti8 GPR:$Rt,
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GPR:$Rn, am2offset:$offset))]> {
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// {13} 1 == Rm, 0 == imm12
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// {12} isAdd
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// {11-0} imm12/Rm
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bits<14> offset;
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bits<4> Rn;
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let Inst{25} = offset{13};
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let Inst{23} = offset{12};
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let Inst{19-16} = Rn;
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let Inst{11-0} = offset{11-0};
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}
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def STRB_POST: AI2ldstidx<0, 1, 0, (outs GPR:$base_wb),
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(ins GPR:$src, GPR:$base,am2offset:$offset),
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def STRB_POST: AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
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(ins GPR:$Rt, GPR:$Rn,am2offset:$offset),
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IndexModePost, StFrm, IIC_iStore_bh_ru,
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"strb", "\t$src, [$base], $offset", "$base = $base_wb",
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[(set GPR:$base_wb, (post_truncsti8 GPR:$src,
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GPR:$base, am2offset:$offset))]>;
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"strb", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
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[(set GPR:$Rn_wb, (post_truncsti8 GPR:$Rt,
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GPR:$Rn, am2offset:$offset))]> {
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// {13} 1 == Rm, 0 == imm12
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// {12} isAdd
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// {11-0} imm12/Rm
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bits<14> offset;
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bits<4> Rn;
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let Inst{25} = offset{13};
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let Inst{23} = offset{12};
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let Inst{19-16} = Rn;
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let Inst{11-0} = offset{11-0};
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}
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// For disassembly only
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def STRD_PRE : AI3stdpr<(outs GPR:$base_wb),
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@ -101,6 +101,29 @@ public:
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case ARM_AM::ib: return 3;
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}
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}
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/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
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///
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unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
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switch (ShOpc) {
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default: llvm_unreachable("Unknown shift opc!");
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case ARM_AM::no_shift:
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case ARM_AM::lsl: return 0;
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case ARM_AM::lsr: return 1;
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case ARM_AM::asr: return 2;
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case ARM_AM::ror:
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case ARM_AM::rrx: return 3;
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}
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return 0;
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}
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/// getAddrMode2OpValue - Return encoding for addrmode2 operands.
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uint32_t getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
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uint32_t getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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/// getAddrMode3OffsetOpValue - Return encoding for am3offset operands.
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uint32_t getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const;
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@ -380,24 +403,10 @@ getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
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const MCOperand &MO2 = MI.getOperand(OpIdx+2);
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unsigned Rn = getARMRegisterNumbering(MO.getReg());
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unsigned Rm = getARMRegisterNumbering(MO1.getReg());
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ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
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unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
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bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
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unsigned SBits;
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// LSL - 00
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// LSR - 01
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// ASR - 10
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// ROR - 11
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switch (ShOp) {
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default: llvm_unreachable("Unknown shift opc!");
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case ARM_AM::no_shift:
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assert(ShImm == 0 && "Non-zero shift amount with no shift type!");
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// fall through
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case ARM_AM::lsl: SBits = 0x0; break;
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case ARM_AM::lsr: SBits = 0x1; break;
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case ARM_AM::asr: SBits = 0x2; break;
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case ARM_AM::ror: SBits = 0x3; break;
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}
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ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
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unsigned SBits = getShiftOp(ShOp);
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// {16-13} = Rn
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// {12} = isAdd
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@ -415,6 +424,42 @@ getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
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return Binary;
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}
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uint32_t ARMMCCodeEmitter::
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getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const {
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// {17-14} Rn
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// {13} 1 == imm12, 0 == Rm
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// {12} isAdd
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// {11-0} imm12/Rm
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const MCOperand &MO = MI.getOperand(OpIdx);
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unsigned Rn = getARMRegisterNumbering(MO.getReg());
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uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
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Binary |= Rn << 14;
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return Binary;
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}
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uint32_t ARMMCCodeEmitter::
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getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const {
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// {13} 1 == imm12, 0 == Rm
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// {12} isAdd
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// {11-0} imm12/Rm
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const MCOperand &MO = MI.getOperand(OpIdx);
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const MCOperand &MO1 = MI.getOperand(OpIdx+1);
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unsigned Imm = MO1.getImm();
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bool isAdd = ARM_AM::getAM2Op(Imm) == ARM_AM::add;
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bool isReg = MO.getReg() != 0;
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uint32_t Binary = ARM_AM::getAM2Offset(Imm);
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// if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm12
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if (isReg) {
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ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
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Binary <<= 7; // Shift amount is bits [11:7]
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Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
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Binary |= getARMRegisterNumbering(MO.getReg()); // Rm is bits [3:0]
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}
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return Binary | (isAdd << 12) | (isReg << 13);
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}
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uint32_t ARMMCCodeEmitter::
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getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx,
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SmallVectorImpl<MCFixup> &Fixups) const {
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