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Use MachineOperand::getImm instead of MachineOperand::getImmedValue. Likewise setImmedValue -> setImm

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45453 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2007-12-30 20:49:49 +00:00
parent a9d059693b
commit 9a1ceaedc2
31 changed files with 156 additions and 159 deletions
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26
lib/Target/ARM/ARMAsmPrinter.cpp
View File

@ -271,7 +271,7 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
if (!Modifier || strcmp(Modifier, "no_hash") != 0)
O << "#";
O << (int)MO.getImmedValue();
O << (int)MO.getImm();
break;
}
case MachineOperand::MO_MachineBasicBlock:
@ -351,7 +351,7 @@ static void printSOImm(std::ostream &O, int64_t V, const TargetAsmInfo *TAI) {
void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
const MachineOperand &MO = MI->getOperand(OpNum);
assert(MO.isImmediate() && "Not a valid so_imm value!");
printSOImm(O, MO.getImmedValue(), TAI);
printSOImm(O, MO.getImm(), TAI);
}
/// printSOImm2PartOperand - SOImm is broken into two pieces using a mov
@ -359,8 +359,8 @@ void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
const MachineOperand &MO = MI->getOperand(OpNum);
assert(MO.isImmediate() && "Not a valid so_imm value!");
unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImmedValue());
unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImmedValue());
unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
printSOImm(O, ARM_AM::getSOImmVal(V1), TAI);
O << "\n\torr";
printPredicateOperand(MI, 2);
@ -387,7 +387,7 @@ void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
// Print the shift opc.
O << ", "
<< ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImmedValue()))
<< ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
<< " ";
if (MO2.getReg()) {
@ -426,7 +426,7 @@ void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
O << ", "
<< ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImmedValue()))
<< ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
<< " #" << ShImm;
O << "]";
}
@ -449,7 +449,7 @@ void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){
if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
O << ", "
<< ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImmedValue()))
<< ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
<< " #" << ShImm;
}
@ -617,7 +617,7 @@ void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
}
void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int opNum) {
ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(opNum).getImmedValue();
ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(opNum).getImm();
if (CC != ARMCC::AL)
O << ARMCondCodeToString(CC);
}
@ -631,7 +631,7 @@ void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int opNum){
}
void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int opNum) {
int Id = (int)MI->getOperand(opNum).getImmedValue();
int Id = (int)MI->getOperand(opNum).getImm();
O << TAI->getPrivateGlobalPrefix() << "PC" << Id;
}
@ -677,7 +677,7 @@ void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNo) {
const MachineOperand &MO2 = MI->getOperand(OpNo+1); // Unique Id
unsigned JTI = MO1.getJumpTableIndex();
O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
<< '_' << JTI << '_' << MO2.getImmedValue() << ":\n";
<< '_' << JTI << '_' << MO2.getImm() << ":\n";
const char *JTEntryDirective = TAI->getJumpTableDirective();
if (!JTEntryDirective)
@ -692,19 +692,19 @@ void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNo) {
for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
MachineBasicBlock *MBB = JTBBs[i];
if (UseSet && JTSets.insert(MBB).second)
printPICJumpTableSetLabel(JTI, MO2.getImmedValue(), MBB);
printPICJumpTableSetLabel(JTI, MO2.getImm(), MBB);
O << JTEntryDirective << ' ';
if (UseSet)
O << TAI->getPrivateGlobalPrefix() << getFunctionNumber()
<< '_' << JTI << '_' << MO2.getImmedValue()
<< '_' << JTI << '_' << MO2.getImm()
<< "_set_" << MBB->getNumber();
else if (TM.getRelocationModel() == Reloc::PIC_) {
printBasicBlockLabel(MBB, false, false);
// If the arch uses custom Jump Table directives, don't calc relative to JT
if (!TAI->getJumpTableDirective())
O << '-' << TAI->getPrivateGlobalPrefix() << "JTI"
<< getFunctionNumber() << '_' << JTI << '_' << MO2.getImmedValue();
<< getFunctionNumber() << '_' << JTI << '_' << MO2.getImm();
} else
printBasicBlockLabel(MBB, false, false);
if (i != e-1)

10
lib/Target/ARM/ARMCodeEmitter.cpp
View File

@ -111,7 +111,7 @@ unsigned Emitter::getBaseOpcodeFor(const TargetInstrDescriptor *TID) {
/// machine operand.
int Emitter::getShiftOp(const MachineOperand &MO) {
unsigned ShiftOp = 0x0;
switch(ARM_AM::getAM2ShiftOpc(MO.getImmedValue())) {
switch(ARM_AM::getAM2ShiftOpc(MO.getImm())) {
default: assert(0 && "Unknown shift opc!");
case ARM_AM::asr:
ShiftOp = 0X2;
@ -137,7 +137,7 @@ int Emitter::getMachineOpValue(const MachineInstr &MI, unsigned OpIndex) {
assert(MRegisterInfo::isPhysicalRegister(MO.getReg()));
rv = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
} else if (MO.isImmediate()) {
rv = MO.getImmedValue();
rv = MO.getImm();
} else if (MO.isGlobalAddress()) {
emitGlobalAddressForCall(MO.getGlobal(), false);
} else if (MO.isExternalSymbol()) {
@ -412,7 +412,7 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
Value |= 1 << ARMII::I_BitShift;
// set immed_8 field
const MachineOperand &MO = MI.getOperand(OperandIndex);
op = ARM_AM::getSOImmVal(MO.getImmedValue());
op = ARM_AM::getSOImmVal(MO.getImm());
Value |= op;
break;
@ -441,7 +441,7 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
// LSR - 011 if it is in register shifts encoding; 010, otherwise.
// ROR - 111 if it is in register shifts encoding; 110, otherwise.
// RRX - 110 and bit[11:7] clear.
switch(ARM_AM::getSORegShOp(MO2.getImmedValue())) {
switch(ARM_AM::getSORegShOp(MO2.getImm())) {
default: assert(0 && "Unknown shift opc!");
case ARM_AM::asr: {
if(IsShiftByRegister)
@ -475,7 +475,7 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
}
}
// set the field related to shift operations (except rrx).
if(ARM_AM::getSORegShOp(MO2.getImmedValue()) != ARM_AM::rrx)
if(ARM_AM::getSORegShOp(MO2.getImm()) != ARM_AM::rrx)
if(IsShiftByRegister) {
// set the value of bit[11:8] (register Rs).
assert(MRegisterInfo::isPhysicalRegister(MO1.getReg()));

2
lib/Target/ARM/ARMConstantIslandPass.cpp
View File

@ -1188,7 +1188,7 @@ ARMConstantIslands::FixUpConditionalBr(MachineFunction &Fn, ImmBranch &Br) {
// bge L2
// b L1
// L2:
ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(1).getImmedValue();
ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(1).getImm();
CC = ARMCC::getOppositeCondition(CC);
unsigned CCReg = MI->getOperand(2).getReg();

20
lib/Target/ARM/ARMInstrInfo.cpp
View File

@ -70,7 +70,7 @@ unsigned ARMInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) co
MI->getOperand(2).isRegister() &&
MI->getOperand(3).isImmediate() &&
MI->getOperand(2).getReg() == 0 &&
MI->getOperand(3).getImmedValue() == 0) {
MI->getOperand(3).getImm() == 0) {
FrameIndex = MI->getOperand(1).getFrameIndex();
return MI->getOperand(0).getReg();
}
@ -79,7 +79,7 @@ unsigned ARMInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) co
case ARM::FLDS:
if (MI->getOperand(1).isFrameIndex() &&
MI->getOperand(2).isImmediate() &&
MI->getOperand(2).getImmedValue() == 0) {
MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getFrameIndex();
return MI->getOperand(0).getReg();
}
@ -87,7 +87,7 @@ unsigned ARMInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) co
case ARM::tRestore:
if (MI->getOperand(1).isFrameIndex() &&
MI->getOperand(2).isImmediate() &&
MI->getOperand(2).getImmedValue() == 0) {
MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getFrameIndex();
return MI->getOperand(0).getReg();
}
@ -104,7 +104,7 @@ unsigned ARMInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) con
MI->getOperand(2).isRegister() &&
MI->getOperand(3).isImmediate() &&
MI->getOperand(2).getReg() == 0 &&
MI->getOperand(3).getImmedValue() == 0) {
MI->getOperand(3).getImm() == 0) {
FrameIndex = MI->getOperand(1).getFrameIndex();
return MI->getOperand(0).getReg();
}
@ -113,7 +113,7 @@ unsigned ARMInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) con
case ARM::FSTS:
if (MI->getOperand(1).isFrameIndex() &&
MI->getOperand(2).isImmediate() &&
MI->getOperand(2).getImmedValue() == 0) {
MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getFrameIndex();
return MI->getOperand(0).getReg();
}
@ -121,7 +121,7 @@ unsigned ARMInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) con
case ARM::tSpill:
if (MI->getOperand(1).isFrameIndex() &&
MI->getOperand(2).isImmediate() &&
MI->getOperand(2).getImmedValue() == 0) {
MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getFrameIndex();
return MI->getOperand(0).getReg();
}
@ -461,7 +461,7 @@ ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
bool ARMInstrInfo::isPredicated(const MachineInstr *MI) const {
int PIdx = MI->findFirstPredOperandIdx();
return PIdx != -1 && MI->getOperand(PIdx).getImmedValue() != ARMCC::AL;
return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
}
bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
@ -477,7 +477,7 @@ bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
int PIdx = MI->findFirstPredOperandIdx();
if (PIdx != -1) {
MachineOperand &PMO = MI->getOperand(PIdx);
PMO.setImm(Pred[0].getImmedValue());
PMO.setImm(Pred[0].getImm());
MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
return true;
}
@ -490,8 +490,8 @@ ARMInstrInfo::SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
if (Pred1.size() > 2 || Pred2.size() > 2)
return false;
ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImmedValue();
ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImmedValue();
ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
if (CC1 == CC2)
return true;

2
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
View File

@ -255,7 +255,7 @@ static ARMCC::CondCodes getInstrPredicate(MachineInstr *MI, unsigned &PredReg) {
}
PredReg = MI->getOperand(PIdx+1).getReg();
return (ARMCC::CondCodes)MI->getOperand(PIdx).getImmedValue();
return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
}
static inline bool isMatchingDecrement(MachineInstr *MI, unsigned Base,

16
lib/Target/ARM/ARMRegisterInfo.cpp
View File

@ -321,8 +321,8 @@ void ARMRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
const MachineInstr *Orig) const {
if (Orig->getOpcode() == ARM::MOVi2pieces) {
emitLoadConstPool(MBB, I, DestReg,
Orig->getOperand(1).getImmedValue(),
(ARMCC::CondCodes)Orig->getOperand(2).getImmedValue(),
Orig->getOperand(1).getImm(),
(ARMCC::CondCodes)Orig->getOperand(2).getImm(),
Orig->getOperand(3).getReg(),
TII, false);
return;
@ -360,7 +360,7 @@ MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI,
if (MI->getOperand(4).getReg() == ARM::CPSR)
// If it is updating CPSR, then it cannot be foled.
break;
unsigned Pred = MI->getOperand(2).getImmedValue();
unsigned Pred = MI->getOperand(2).getImm();
unsigned PredReg = MI->getOperand(3).getReg();
if (OpNum == 0) { // move -> store
unsigned SrcReg = MI->getOperand(1).getReg();
@ -392,7 +392,7 @@ MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI,
break;
}
case ARM::FCPYS: {
unsigned Pred = MI->getOperand(2).getImmedValue();
unsigned Pred = MI->getOperand(2).getImm();
unsigned PredReg = MI->getOperand(3).getReg();
if (OpNum == 0) { // move -> store
unsigned SrcReg = MI->getOperand(1).getReg();
@ -406,7 +406,7 @@ MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr *MI,
break;
}
case ARM::FCPYD: {
unsigned Pred = MI->getOperand(2).getImmedValue();
unsigned Pred = MI->getOperand(2).getImm();
unsigned PredReg = MI->getOperand(3).getReg();
if (OpNum == 0) { // move -> store
unsigned SrcReg = MI->getOperand(1).getReg();
@ -792,7 +792,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
// ADJCALLSTACKDOWN -> sub, sp, sp, amount
// ADJCALLSTACKUP -> add, sp, sp, amount
MachineInstr *Old = I;
unsigned Amount = Old->getOperand(0).getImmedValue();
unsigned Amount = Old->getOperand(0).getImm();
if (Amount != 0) {
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
// We need to keep the stack aligned properly. To do this, we round the
@ -805,7 +805,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
unsigned Opc = Old->getOpcode();
bool isThumb = AFI->isThumbFunction();
ARMCC::CondCodes Pred = isThumb
? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(1).getImmedValue();
? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(1).getImm();
if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
// Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
unsigned PredReg = isThumb ? 0 : Old->getOperand(2).getReg();
@ -1160,7 +1160,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj);
int PIdx = MI.findFirstPredOperandIdx();
ARMCC::CondCodes Pred = (PIdx == -1)
? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImmedValue();
? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg,
isSub ? -Offset : Offset, Pred, PredReg, TII);

4
lib/Target/Alpha/AlphaAsmPrinter.cpp
View File

@ -78,8 +78,8 @@ void AlphaAsmPrinter::printOperand(const MachineInstr *MI, int opNum)
assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
} else if (MO.isImmediate()) {
O << MO.getImmedValue();
assert(MO.getImmedValue() < (1 << 30));
O << MO.getImm();
assert(MO.getImm() < (1 << 30));
} else {
printOp(MO);
}

12
lib/Target/Alpha/AlphaCodeEmitter.cpp
View File

@ -151,7 +151,7 @@ int AlphaCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
if (MO.isRegister()) {
rv = getAlphaRegNumber(MO.getReg());
} else if (MO.isImmediate()) {
rv = MO.getImmedValue();
rv = MO.getImm();
} else if (MO.isGlobalAddress() || MO.isExternalSymbol()
|| MO.isConstantPoolIndex()) {
DOUT << MO << " is a relocated op for " << MI << "\n";
@ -187,7 +187,7 @@ int AlphaCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
case Alpha::LDAg:
case Alpha::LDAHg:
Reloc = Alpha::reloc_gpdist;
Offset = MI.getOperand(3).getImmedValue();
Offset = MI.getOperand(3).getImm();
break;
default:
assert(0 && "unknown relocatable instruction");
@ -195,12 +195,12 @@ int AlphaCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
}
if (MO.isGlobalAddress())
MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
Reloc, MO.getGlobal(), Offset,
false, useGOT));
Reloc, MO.getGlobal(), Offset,
false, useGOT));
else if (MO.isExternalSymbol())
MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
Reloc, MO.getSymbolName(), Offset,
true));
Reloc, MO.getSymbolName(),
Offset, true));
else
MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
Reloc, MO.getConstantPoolIndex(),

16
lib/Target/Alpha/AlphaLLRP.cpp
View File

@ -67,11 +67,9 @@ namespace {
case Alpha::STW: case Alpha::STB:
case Alpha::STT: case Alpha::STS:
if (MI->getOperand(2).getReg() == Alpha::R30) {
if (prev[0]
&& prev[0]->getOperand(2).getReg() ==
MI->getOperand(2).getReg()
&& prev[0]->getOperand(1).getImmedValue() ==
MI->getOperand(1).getImmedValue()) {
if (prev[0] &&
prev[0]->getOperand(2).getReg() == MI->getOperand(2).getReg()&&
prev[0]->getOperand(1).getImm() == MI->getOperand(1).getImm()){
prev[0] = prev[1];
prev[1] = prev[2];
prev[2] = 0;
@ -83,8 +81,8 @@ namespace {
} else if (prev[1]
&& prev[1]->getOperand(2).getReg() ==
MI->getOperand(2).getReg()
&& prev[1]->getOperand(1).getImmedValue() ==
MI->getOperand(1).getImmedValue()) {
&& prev[1]->getOperand(1).getImm() ==
MI->getOperand(1).getImm()) {
prev[0] = prev[2];
prev[1] = prev[2] = 0;
BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31)
@ -98,8 +96,8 @@ namespace {
} else if (prev[2]
&& prev[2]->getOperand(2).getReg() ==
MI->getOperand(2).getReg()
&& prev[2]->getOperand(1).getImmedValue() ==
MI->getOperand(1).getImmedValue()) {
&& prev[2]->getOperand(1).getImm() ==
MI->getOperand(1).getImm()) {
prev[0] = prev[1] = prev[2] = 0;
BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31)
.addReg(Alpha::R31);

2
lib/Target/Alpha/AlphaRegisterInfo.cpp
View File

@ -280,7 +280,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
// 'sub ESP, <amt>' and the adjcallstackdown instruction into 'add ESP,
// <amt>'
MachineInstr *Old = I;
uint64_t Amount = Old->getOperand(0).getImmedValue();
uint64_t Amount = Old->getOperand(0).getImm();
if (Amount != 0) {
// We need to keep the stack aligned properly. To do this, we round the
// amount of space needed for the outgoing arguments up to the next

28
lib/Target/CellSPU/SPUAsmPrinter.cpp
View File

@ -83,7 +83,7 @@ namespace {
assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
} else if (MO.isImmediate()) {
O << MO.getImmedValue();
O << MO.getImm();
} else {
printOp(MO);
}
@ -98,7 +98,7 @@ namespace {
void
printS7ImmOperand(const MachineInstr *MI, unsigned OpNo)
{
int value = MI->getOperand(OpNo).getImmedValue();
int value = MI->getOperand(OpNo).getImm();
value = (value << (32 - 7)) >> (32 - 7);
assert((value >= -(1 << 8) && value <= (1 << 7) - 1)
@ -109,7 +109,7 @@ namespace {
void
printU7ImmOperand(const MachineInstr *MI, unsigned OpNo)
{
unsigned int value = MI->getOperand(OpNo).getImmedValue();
unsigned int value = MI->getOperand(OpNo).getImm();
assert(value < (1 << 8) && "Invalid u7 argument");
O << value;
}
@ -117,7 +117,7 @@ namespace {
void
printMemRegImmS7(const MachineInstr *MI, unsigned OpNo)
{
char value = MI->getOperand(OpNo).getImmedValue();
char value = MI->getOperand(OpNo).getImm();
O << (int) value;
O << "(";
printOperand(MI, OpNo+1);
@ -127,19 +127,19 @@ namespace {
void
printS16ImmOperand(const MachineInstr *MI, unsigned OpNo)
{
O << (short) MI->getOperand(OpNo).getImmedValue();
O << (short) MI->getOperand(OpNo).getImm();
}
void
printU16ImmOperand(const MachineInstr *MI, unsigned OpNo)
{
O << (unsigned short)MI->getOperand(OpNo).getImmedValue();
O << (unsigned short)MI->getOperand(OpNo).getImm();
}
void
printU32ImmOperand(const MachineInstr *MI, unsigned OpNo)
{
O << (unsigned)MI->getOperand(OpNo).getImmedValue();
O << (unsigned)MI->getOperand(OpNo).getImm();
}
void
@ -156,7 +156,7 @@ namespace {
void
printU18ImmOperand(const MachineInstr *MI, unsigned OpNo)
{
unsigned int value = MI->getOperand(OpNo).getImmedValue();
unsigned int value = MI->getOperand(OpNo).getImm();
assert(value <= (1 << 19) - 1 && "Invalid u18 argument");
O << value;
}
@ -164,7 +164,7 @@ namespace {
void
printS10ImmOperand(const MachineInstr *MI, unsigned OpNo)
{
short value = (short) (((int) MI->getOperand(OpNo).getImmedValue() << 16)
short value = (short) (((int) MI->getOperand(OpNo).getImm() << 16)
>> 16);
assert((value >= -(1 << 9) && value <= (1 << 9) - 1)
&& "Invalid s10 argument");
@ -174,7 +174,7 @@ namespace {
void
printU10ImmOperand(const MachineInstr *MI, unsigned OpNo)
{
short value = (short) (((int) MI->getOperand(OpNo).getImmedValue() << 16)
short value = (short) (((int) MI->getOperand(OpNo).getImm() << 16)
>> 16);
assert((value <= (1 << 10) - 1) && "Invalid u10 argument");
O << value;
@ -238,23 +238,23 @@ namespace {
void printROTHNeg7Imm(const MachineInstr *MI, unsigned OpNo) {
if (MI->getOperand(OpNo).isImmediate()) {
int value = (int) MI->getOperand(OpNo).getImmedValue();
int value = (int) MI->getOperand(OpNo).getImm();
assert((value >= 0 && value < 16)
&& "Invalid negated immediate rotate 7-bit argument");
O << -value;
} else {
assert(0 && "Invalid/non-immediate rotate amount in printRotateNeg7Imm");
assert(0 &&"Invalid/non-immediate rotate amount in printRotateNeg7Imm");
}
}
void printROTNeg7Imm(const MachineInstr *MI, unsigned OpNo) {
if (MI->getOperand(OpNo).isImmediate()) {
int value = (int) MI->getOperand(OpNo).getImmedValue();
int value = (int) MI->getOperand(OpNo).getImm();
assert((value >= 0 && value < 32)
&& "Invalid negated immediate rotate 7-bit argument");
O << -value;
} else {
assert(0 && "Invalid/non-immediate rotate amount in printRotateNeg7Imm");
assert(0 &&"Invalid/non-immediate rotate amount in printRotateNeg7Imm");
}
}

8
lib/Target/CellSPU/SPUInstrInfo.cpp
View File

@ -64,7 +64,7 @@ SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
MI.getOperand(1).isRegister() &&
MI.getOperand(2).isImmediate() &&
"invalid SPU ORI/ORHI/ORBI/AHI/AI/SFI/SFHI instruction!");
if (MI.getOperand(2).getImmedValue() == 0) {
if (MI.getOperand(2).getImm() == 0) {
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
@ -77,7 +77,7 @@ SPUInstrInfo::isMoveInstr(const MachineInstr& MI,
(MI.getOperand(1).isRegister() ||
MI.getOperand(1).isFrameIndex()) &&
(MI.getOperand(2).isImmediate() &&
MI.getOperand(2).getImmedValue() == 0)) {
MI.getOperand(2).getImm() == 0)) {
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
@ -137,7 +137,7 @@ SPUInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const {
case SPU::LQXr64:
case SPU::LQXr32:
case SPU::LQXr16:
if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
MI->getOperand(2).isFrameIndex()) {
FrameIndex = MI->getOperand(2).getFrameIndex();
return MI->getOperand(0).getReg();
@ -171,7 +171,7 @@ SPUInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
case SPU::STQXr32:
case SPU::STQXr16:
// case SPU::STQXr8:
if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
MI->getOperand(2).isFrameIndex()) {
FrameIndex = MI->getOperand(2).getFrameIndex();
return MI->getOperand(0).getReg();

17
lib/Target/CellSPU/SPURegisterInfo.cpp
View File

@ -263,11 +263,11 @@ void SPURegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
MachineOperand &MO = Addr[i];
if (MO.isRegister())
MIB.addReg(MO.getReg());
MIB.addReg(MO.getReg());
else if (MO.isImmediate())
MIB.addImm(MO.getImmedValue());
MIB.addImm(MO.getImm());
else
MIB.addFrameIndex(MO.getFrameIndex());
MIB.addFrameIndex(MO.getFrameIndex());
}
NewMIs.push_back(MIB);
}
@ -349,11 +349,11 @@ void SPURegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
MachineOperand &MO = Addr[i];
if (MO.isRegister())
MIB.addReg(MO.getReg());
MIB.addReg(MO.getReg());
else if (MO.isImmediate())
MIB.addImm(MO.getImmedValue());
MIB.addImm(MO.getImm());
else
MIB.addFrameIndex(MO.getFrameIndex());
MIB.addFrameIndex(MO.getFrameIndex());
}
NewMIs.push_back(MIB);
}
@ -610,10 +610,9 @@ SPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
MachineOperand &MO = MI.getOperand(OpNo);
// Offset is biased by $lr's slot at the bottom.
Offset += MO.getImmedValue() + MFI->getStackSize()
+ SPUFrameInfo::minStackSize();
Offset += MO.getImm() + MFI->getStackSize() + SPUFrameInfo::minStackSize();
assert((Offset & 0xf) == 0
&& "16-byte alignment violated in SPURegisterInfo::eliminateFrameIndex");
&& "16-byte alignment violated in eliminateFrameIndex");
// Replace the FrameIndex with base register with $sp (aka $r1)
SPOp.ChangeToRegister(SPU::R1, false);

12
lib/Target/IA64/IA64AsmPrinter.cpp
View File

@ -62,22 +62,22 @@ namespace {
}
void printS8ImmOperand(const MachineInstr *MI, unsigned OpNo) {
int val=(unsigned int)MI->getOperand(OpNo).getImmedValue();
int val=(unsigned int)MI->getOperand(OpNo).getImm();
if(val>=128) val=val-256; // if negative, flip sign
O << val;
}
void printS14ImmOperand(const MachineInstr *MI, unsigned OpNo) {
int val=(unsigned int)MI->getOperand(OpNo).getImmedValue();
int val=(unsigned int)MI->getOperand(OpNo).getImm();
if(val>=8192) val=val-16384; // if negative, flip sign
O << val;
}
void printS22ImmOperand(const MachineInstr *MI, unsigned OpNo) {
int val=(unsigned int)MI->getOperand(OpNo).getImmedValue();
int val=(unsigned int)MI->getOperand(OpNo).getImm();
if(val>=2097152) val=val-4194304; // if negative, flip sign
O << val;
}
void printU64ImmOperand(const MachineInstr *MI, unsigned OpNo) {
O << (uint64_t)MI->getOperand(OpNo).getImmedValue();
O << (uint64_t)MI->getOperand(OpNo).getImm();
}
void printS64ImmOperand(const MachineInstr *MI, unsigned OpNo) {
// XXX : nasty hack to avoid GPREL22 "relocation truncated to fit" linker
@ -90,7 +90,7 @@ namespace {
// If it's an immediate, print it the old fashioned way. If it's
// not, we print it as a constant pool index.
if(MI->getOperand(OpNo).isImmediate()) {
O << (int64_t)MI->getOperand(OpNo).getImmedValue();
O << (int64_t)MI->getOperand(OpNo).getImm();
} else { // this is a constant pool reference: FIXME: assert this
printOp(MI->getOperand(OpNo));
}
@ -172,7 +172,7 @@ void IA64AsmPrinter::printOp(const MachineOperand &MO,
return;
case MachineOperand::MO_Immediate:
O << MO.getImmedValue();
O << MO.getImm();
return;
case MachineOperand::MO_MachineBasicBlock:
printBasicBlockLabel(MO.getMachineBasicBlock());

6
lib/Target/IA64/IA64RegisterInfo.cpp
View File

@ -84,7 +84,7 @@ void IA64RegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
if (MO.isRegister())
MIB.addReg(MO.getReg());
else if (MO.isImmediate())
MIB.addImm(MO.getImmedValue());
MIB.addImm(MO.getImm());
else
MIB.addFrameIndex(MO.getFrameIndex());
}
@ -136,7 +136,7 @@ void IA64RegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
if (MO.isRegister())
MIB.addReg(MO.getReg());
else if (MO.isImmediate())
MIB.addImm(MO.getImmedValue());
MIB.addImm(MO.getImm());
else
MIB.addFrameIndex(MO.getFrameIndex());
}
@ -220,7 +220,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
// 'sub SP, <amt>' and the adjcallstackdown instruction into 'add SP,
// <amt>'
MachineInstr *Old = I;
unsigned Amount = Old->getOperand(0).getImmedValue();
unsigned Amount = Old->getOperand(0).getImm();
if (Amount != 0) {
// We need to keep the stack aligned properly. To do this, we round the
// amount of space needed for the outgoing arguments up to the next

4
lib/Target/Mips/MipsAsmPrinter.cpp
View File

@ -374,9 +374,9 @@ printOperand(const MachineInstr *MI, int opNum)
case MachineOperand::MO_Immediate:
if ((MI->getOpcode() == Mips::SLTiu) || (MI->getOpcode() == Mips::ORi) ||
(MI->getOpcode() == Mips::LUi) || (MI->getOpcode() == Mips::ANDi))
O << (unsigned short int)MO.getImmedValue();
O << (unsigned short int)MO.getImm();
else
O << (short int)MO.getImmedValue();
O << (short int)MO.getImm();
break;
case MachineOperand::MO_MachineBasicBlock:

2
lib/Target/Mips/MipsInstrInfo.cpp
View File

@ -25,7 +25,7 @@ MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
TM(tm), RI(*this) {}
static bool isZeroImm(const MachineOperand &op) {
return op.isImmediate() && op.getImmedValue() == 0;
return op.isImmediate() && op.getImm() == 0;
}
/// Return true if the instruction is a register to register move and

4
lib/Target/Mips/MipsRegisterInfo.cpp
View File

@ -109,7 +109,7 @@ void MipsRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
if (MO.isRegister())
MIB.addReg(MO.getReg());
else if (MO.isImmediate())
MIB.addImm(MO.getImmedValue());
MIB.addImm(MO.getImm());
else
MIB.addFrameIndex(MO.getFrameIndex());
}
@ -140,7 +140,7 @@ void MipsRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
if (MO.isRegister())
MIB.addReg(MO.getReg());
else if (MO.isImmediate())
MIB.addImm(MO.getImmedValue());
MIB.addImm(MO.getImm());
else
MIB.addFrameIndex(MO.getFrameIndex());
}

28
lib/Target/PowerPC/PPCAsmPrinter.cpp
View File

@ -124,7 +124,7 @@ namespace {
if (MO.isRegister()) {
printRegister(MO, false);
} else if (MO.isImmediate()) {
O << MO.getImmedValue();
O << MO.getImm();
} else {
printOp(MO);
}
@ -137,29 +137,29 @@ namespace {
void printS5ImmOperand(const MachineInstr *MI, unsigned OpNo) {
char value = MI->getOperand(OpNo).getImmedValue();
char value = MI->getOperand(OpNo).getImm();
value = (value << (32-5)) >> (32-5);
O << (int)value;
}
void printU5ImmOperand(const MachineInstr *MI, unsigned OpNo) {
unsigned char value = MI->getOperand(OpNo).getImmedValue();
unsigned char value = MI->getOperand(OpNo).getImm();
assert(value <= 31 && "Invalid u5imm argument!");
O << (unsigned int)value;
}
void printU6ImmOperand(const MachineInstr *MI, unsigned OpNo) {
unsigned char value = MI->getOperand(OpNo).getImmedValue();
unsigned char value = MI->getOperand(OpNo).getImm();
assert(value <= 63 && "Invalid u6imm argument!");
O << (unsigned int)value;
}
void printS16ImmOperand(const MachineInstr *MI, unsigned OpNo) {
O << (short)MI->getOperand(OpNo).getImmedValue();
O << (short)MI->getOperand(OpNo).getImm();
}
void printU16ImmOperand(const MachineInstr *MI, unsigned OpNo) {
O << (unsigned short)MI->getOperand(OpNo).getImmedValue();
O << (unsigned short)MI->getOperand(OpNo).getImm();
}
void printS16X4ImmOperand(const MachineInstr *MI, unsigned OpNo) {
if (MI->getOperand(OpNo).isImmediate()) {
O << (short)(MI->getOperand(OpNo).getImmedValue()*4);
O << (short)(MI->getOperand(OpNo).getImm()*4);
} else {
O << "lo16(";
printOp(MI->getOperand(OpNo));
@ -173,7 +173,7 @@ namespace {
// Branches can take an immediate operand. This is used by the branch
// selection pass to print $+8, an eight byte displacement from the PC.
if (MI->getOperand(OpNo).isImmediate()) {
O << "$+" << MI->getOperand(OpNo).getImmedValue()*4;
O << "$+" << MI->getOperand(OpNo).getImm()*4;
} else {
printOp(MI->getOperand(OpNo));
}
@ -205,7 +205,7 @@ namespace {
printOp(MI->getOperand(OpNo));
}
void printAbsAddrOperand(const MachineInstr *MI, unsigned OpNo) {
O << (int)MI->getOperand(OpNo).getImmedValue()*4;
O << (int)MI->getOperand(OpNo).getImm()*4;
}
void printPICLabel(const MachineInstr *MI, unsigned OpNo) {
O << "\"L" << getFunctionNumber() << "$pb\"\n";
@ -509,9 +509,9 @@ void PPCAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
// Check for slwi/srwi mnemonics.
if (MI->getOpcode() == PPC::RLWINM) {
bool FoundMnemonic = false;
unsigned char SH = MI->getOperand(2).getImmedValue();
unsigned char MB = MI->getOperand(3).getImmedValue();
unsigned char ME = MI->getOperand(4).getImmedValue();
unsigned char SH = MI->getOperand(2).getImm();
unsigned char MB = MI->getOperand(3).getImm();
unsigned char ME = MI->getOperand(4).getImm();
if (SH <= 31 && MB == 0 && ME == (31-SH)) {
O << "slwi "; FoundMnemonic = true;
}
@ -536,8 +536,8 @@ void PPCAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
return;
}
} else if (MI->getOpcode() == PPC::RLDICR) {
unsigned char SH = MI->getOperand(2).getImmedValue();
unsigned char ME = MI->getOperand(3).getImmedValue();
unsigned char SH = MI->getOperand(2).getImm();
unsigned char ME = MI->getOperand(3).getImm();
// rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
if (63-SH == ME) {
O << "sldi ";

2
lib/Target/PowerPC/PPCCodeEmitter.cpp
View File

@ -131,7 +131,7 @@ int PPCCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
rv = 0x80 >> rv;
}
} else if (MO.isImmediate()) {
rv = MO.getImmedValue();
rv = MO.getImm();
} else if (MO.isGlobalAddress() || MO.isExternalSymbol() ||
MO.isConstantPoolIndex() || MO.isJumpTableIndex()) {
unsigned Reloc = 0;

18
lib/Target/PowerPC/PPCInstrInfo.cpp
View File

@ -54,7 +54,7 @@ bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
MI.getOperand(0).isRegister() &&
MI.getOperand(2).isImmediate() &&
"invalid PPC ADDI instruction!");
if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImmedValue()==0) {
if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImm() == 0) {
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
@ -65,7 +65,7 @@ bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
MI.getOperand(1).isRegister() &&
MI.getOperand(2).isImmediate() &&
"invalid PPC ORI instruction!");
if (MI.getOperand(2).getImmedValue()==0) {
if (MI.getOperand(2).getImm() == 0) {
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
@ -99,7 +99,7 @@ unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI,
case PPC::LWZ:
case PPC::LFS:
case PPC::LFD:
if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
MI->getOperand(2).isFrameIndex()) {
FrameIndex = MI->getOperand(2).getFrameIndex();
return MI->getOperand(0).getReg();
@ -117,7 +117,7 @@ unsigned PPCInstrInfo::isStoreToStackSlot(MachineInstr *MI,
case PPC::STW:
case PPC::STFS:
case PPC::STFD:
if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImmedValue() &&
if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
MI->getOperand(2).isFrameIndex()) {
FrameIndex = MI->getOperand(2).getFrameIndex();
return MI->getOperand(0).getReg();
@ -135,7 +135,7 @@ MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const {
return TargetInstrInfo::commuteInstruction(MI);
// Cannot commute if it has a non-zero rotate count.
if (MI->getOperand(3).getImmedValue() != 0)
if (MI->getOperand(3).getImm() != 0)
return 0;
// If we have a zero rotate count, we have:
@ -162,10 +162,10 @@ MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const {
MI->getOperand(1).unsetIsKill();
// Swap the mask around.
unsigned MB = MI->getOperand(4).getImmedValue();
unsigned ME = MI->getOperand(5).getImmedValue();
MI->getOperand(4).setImmedValue((ME+1) & 31);
MI->getOperand(5).setImmedValue((MB-1) & 31);
unsigned MB = MI->getOperand(4).getImm();
unsigned ME = MI->getOperand(5).getImm();
MI->getOperand(4).setImm((ME+1) & 31);
MI->getOperand(5).setImm((MB-1) & 31);
return MI;
}

8
lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -214,7 +214,7 @@ void PPCRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
if (MO.isRegister())
MIB.addReg(MO.getReg());
else if (MO.isImmediate())
MIB.addImm(MO.getImmedValue());
MIB.addImm(MO.getImm());
else
MIB.addFrameIndex(MO.getFrameIndex());
}
@ -324,7 +324,7 @@ void PPCRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
if (MO.isRegister())
MIB.addReg(MO.getReg());
else if (MO.isImmediate())
MIB.addImm(MO.getImmedValue());
MIB.addImm(MO.getImm());
else
MIB.addFrameIndex(MO.getFrameIndex());
}
@ -802,9 +802,9 @@ void PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
// Now add the frame object offset to the offset from r1.
int Offset = MFI->getObjectOffset(FrameIndex);
if (!isIXAddr)
Offset += MI.getOperand(OffsetOperandNo).getImmedValue();
Offset += MI.getOperand(OffsetOperandNo).getImm();
else
Offset += MI.getOperand(OffsetOperandNo).getImmedValue() << 2;
Offset += MI.getOperand(OffsetOperandNo).getImm() << 2;
// If we're not using a Frame Pointer that has been set to the value of the
// SP before having the stack size subtracted from it, then add the stack size

6
lib/Target/Sparc/SparcAsmPrinter.cpp
View File

@ -152,7 +152,7 @@ void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
break;
case MachineOperand::MO_Immediate:
O << (int)MO.getImmedValue();
O << (int)MO.getImm();
break;
case MachineOperand::MO_MachineBasicBlock:
printBasicBlockLabel(MO.getMachineBasicBlock());
@ -188,7 +188,7 @@ void SparcAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum,
MI->getOperand(opNum+1).getReg() == SP::G0)
return; // don't print "+%g0"
if (MI->getOperand(opNum+1).isImmediate() &&
MI->getOperand(opNum+1).getImmedValue() == 0)
MI->getOperand(opNum+1).getImm() == 0)
return; // don't print "+0"
O << "+";
@ -203,7 +203,7 @@ void SparcAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum,
}
void SparcAsmPrinter::printCCOperand(const MachineInstr *MI, int opNum) {
int CC = (int)MI->getOperand(opNum).getImmedValue();
int CC = (int)MI->getOperand(opNum).getImm();
O << SPARCCondCodeToString((SPCC::CondCodes)CC);
}

2
lib/Target/Sparc/SparcISelDAGToDAG.cpp
View File

@ -912,7 +912,7 @@ SparcTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
break;
}
CC = (SPCC::CondCodes)MI->getOperand(3).getImmedValue();
CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
// To "insert" a SELECT_CC instruction, we actually have to insert the diamond
// control-flow pattern. The incoming instruction knows the destination vreg

6
lib/Target/Sparc/SparcInstrInfo.cpp
View File

@ -24,7 +24,7 @@ SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
}
static bool isZeroImm(const MachineOperand &op) {
return op.isImmediate() && op.getImmedValue() == 0;
return op.isImmediate() && op.getImm() == 0;
}
/// Return true if the instruction is a register to register move and
@ -71,7 +71,7 @@ unsigned SparcInstrInfo::isLoadFromStackSlot(MachineInstr *MI,
MI->getOpcode() == SP::LDFri ||
MI->getOpcode() == SP::LDDFri) {
if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
MI->getOperand(2).getImmedValue() == 0) {
MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getFrameIndex();
return MI->getOperand(0).getReg();
}
@ -90,7 +90,7 @@ unsigned SparcInstrInfo::isStoreToStackSlot(MachineInstr *MI,
MI->getOpcode() == SP::STFri ||
MI->getOpcode() == SP::STDFri) {
if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
MI->getOperand(1).getImmedValue() == 0) {
MI->getOperand(1).getImm() == 0) {
FrameIndex = MI->getOperand(0).getFrameIndex();
return MI->getOperand(2).getReg();
}

8
lib/Target/Sparc/SparcRegisterInfo.cpp
View File

@ -68,7 +68,7 @@ void SparcRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
if (MO.isRegister())
MIB.addReg(MO.getReg());
else if (MO.isImmediate())
MIB.addImm(MO.getImmedValue());
MIB.addImm(MO.getImm());
else
MIB.addFrameIndex(MO.getFrameIndex());
}
@ -110,7 +110,7 @@ void SparcRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
if (MO.isRegister())
MIB.addReg(MO.getReg());
else if (MO.isImmediate())
MIB.addImm(MO.getImmedValue());
MIB.addImm(MO.getImm());
else
MIB.addFrameIndex(MO.getFrameIndex());
}
@ -222,7 +222,7 @@ void SparcRegisterInfo::
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const {
MachineInstr &MI = *I;
int Size = MI.getOperand(0).getImmedValue();
int Size = MI.getOperand(0).getImm();
if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
Size = -Size;
if (Size)
@ -246,7 +246,7 @@ void SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
// Addressable stack objects are accessed using neg. offsets from %fp
MachineFunction &MF = *MI.getParent()->getParent();
int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
MI.getOperand(i+1).getImmedValue();
MI.getOperand(i+1).getImm();
// Replace frame index with a frame pointer reference.
if (Offset >= -4096 && Offset <= 4095) {

2
lib/Target/TargetInstrInfo.cpp
View File

@ -72,7 +72,7 @@ bool TargetInstrInfo::PredicateInstruction(MachineInstr *MI,
MO.setReg(Pred[j].getReg());
MadeChange = true;
} else if (MO.isImmediate()) {
MO.setImm(Pred[j].getImmedValue());
MO.setImm(Pred[j].getImm());
MadeChange = true;
} else if (MO.isMachineBasicBlock()) {
MO.setMachineBasicBlock(Pred[j].getMachineBasicBlock());

8
lib/Target/X86/X86ATTAsmPrinter.cpp
View File

@ -229,7 +229,7 @@ void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
if (!Modifier ||
(strcmp(Modifier, "debug") && strcmp(Modifier, "mem")))
O << '$';
O << MO.getImmedValue();
O << MO.getImm();
return;
case MachineOperand::MO_MachineBasicBlock:
printBasicBlockLabel(MO.getMachineBasicBlock());
@ -440,7 +440,7 @@ void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
}
void X86ATTAsmPrinter::printSSECC(const MachineInstr *MI, unsigned Op) {
unsigned char value = MI->getOperand(Op).getImmedValue();
unsigned char value = MI->getOperand(Op).getImm();
assert(value <= 7 && "Invalid ssecc argument!");
switch (value) {
case 0: O << "eq"; break;
@ -467,13 +467,13 @@ void X86ATTAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
DispSpec.isJumpTableIndex()) {
printOperand(MI, Op+3, "mem", NotRIPRel);
} else {
int DispVal = DispSpec.getImmedValue();
int DispVal = DispSpec.getImm();
if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg()))
O << DispVal;
}
if (IndexReg.getReg() || BaseReg.getReg()) {
unsigned ScaleVal = MI->getOperand(Op+1).getImmedValue();
unsigned ScaleVal = MI->getOperand(Op+1).getImm();
unsigned BaseRegOperand = 0, IndexRegOperand = 2;
// There are cases where we can end up with ESP/RSP in the indexreg slot.

4
lib/Target/X86/X86AsmPrinter.h
View File

@ -77,8 +77,8 @@ struct VISIBILITY_HIDDEN X86SharedAsmPrinter : public AsmPrinter {
inline static bool isScale(const MachineOperand &MO) {
return MO.isImmediate() &&
(MO.getImmedValue() == 1 || MO.getImmedValue() == 2 ||
MO.getImmedValue() == 4 || MO.getImmedValue() == 8);
(MO.getImm() == 1 || MO.getImm() == 2 ||
MO.getImm() == 4 || MO.getImm() == 8);
}
inline static bool isMem(const MachineInstr *MI, unsigned Op) {

24
lib/Target/X86/X86InstrInfo.cpp
View File

@ -73,9 +73,9 @@ unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI,
case X86::MMX_MOVQ64rm:
if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() &&
MI->getOperand(2).getImmedValue() == 1 &&
MI->getOperand(2).getImm() == 1 &&
MI->getOperand(3).getReg() == 0 &&
MI->getOperand(4).getImmedValue() == 0) {
MI->getOperand(4).getImm() == 0) {
FrameIndex = MI->getOperand(1).getFrameIndex();
return MI->getOperand(0).getReg();
}
@ -104,9 +104,9 @@ unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI,
case X86::MMX_MOVNTQmr:
if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() &&
MI->getOperand(1).getImmedValue() == 1 &&
MI->getOperand(1).getImm() == 1 &&
MI->getOperand(2).getReg() == 0 &&
MI->getOperand(3).getImmedValue() == 0) {
MI->getOperand(3).getImm() == 0) {
FrameIndex = MI->getOperand(0).getFrameIndex();
return MI->getOperand(4).getReg();
}
@ -136,7 +136,7 @@ bool X86InstrInfo::isReallyTriviallyReMaterializable(MachineInstr *MI) const {
return MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate() &&
MI->getOperand(3).isRegister() && MI->getOperand(4).isConstantPoolIndex() &&
MI->getOperand(1).getReg() == 0 &&
MI->getOperand(2).getImmedValue() == 1 &&
MI->getOperand(2).getImm() == 1 &&
MI->getOperand(3).getReg() == 0;
}
// All other instructions marked M_REMATERIALIZABLE are always trivially
@ -194,7 +194,7 @@ bool X86InstrInfo::isReallySideEffectFree(MachineInstr *MI) const {
MI->getOperand(2).isImmediate() &&
MI->getOperand(3).isRegister() &&
MI->getOperand(4).isGlobalAddress() &&
MI->getOperand(2).getImmedValue() == 1 &&
MI->getOperand(2).getImm() == 1 &&
MI->getOperand(3).getReg() == 0)
return true;
}
@ -217,7 +217,7 @@ bool X86InstrInfo::isReallySideEffectFree(MachineInstr *MI) const {
MI->getOperand(3).isRegister() &&
MI->getOperand(4).isConstantPoolIndex() &&
MI->getOperand(1).getReg() == 0 &&
MI->getOperand(2).getImmedValue() == 1 &&
MI->getOperand(2).getImm() == 1 &&
MI->getOperand(3).getReg() == 0;
}
@ -404,7 +404,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
if (MI->getOperand(2).isImmediate())
NewMI = addRegOffset(BuildMI(get(X86::LEA64r), Dest), Src,
MI->getOperand(2).getImmedValue());
MI->getOperand(2).getImm());
break;
case X86::ADD32ri:
case X86::ADD32ri8:
@ -412,7 +412,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
if (MI->getOperand(2).isImmediate()) {
unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src,
MI->getOperand(2).getImmedValue());
MI->getOperand(2).getImm());
}
break;
case X86::ADD16ri:
@ -421,7 +421,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
if (MI->getOperand(2).isImmediate())
NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src,
MI->getOperand(2).getImmedValue());
MI->getOperand(2).getImm());
break;
case X86::SHL16ri:
if (DisableLEA16) return 0;
@ -429,7 +429,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
case X86::SHL64ri: {
assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImmediate() &&
"Unknown shl instruction!");
unsigned ShAmt = MI->getOperand(2).getImmedValue();
unsigned ShAmt = MI->getOperand(2).getImm();
if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
X86AddressMode AM;
AM.Scale = 1 << ShAmt;
@ -473,7 +473,7 @@ MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
}
unsigned Amt = MI->getOperand(3).getImmedValue();
unsigned Amt = MI->getOperand(3).getImm();
unsigned A = MI->getOperand(0).getReg();
unsigned B = MI->getOperand(1).getReg();
unsigned C = MI->getOperand(2).getReg();

8
lib/Target/X86/X86IntelAsmPrinter.cpp
View File

@ -99,7 +99,7 @@ bool X86IntelAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
}
void X86IntelAsmPrinter::printSSECC(const MachineInstr *MI, unsigned Op) {
unsigned char value = MI->getOperand(Op).getImmedValue();
unsigned char value = MI->getOperand(Op).getImm();
assert(value <= 7 && "Invalid ssecc argument!");
switch (value) {
case 0: O << "eq"; break;
@ -132,7 +132,7 @@ void X86IntelAsmPrinter::printOp(const MachineOperand &MO,
return;
}
case MachineOperand::MO_Immediate:
O << MO.getImmedValue();
O << MO.getImm();
return;
case MachineOperand::MO_MachineBasicBlock:
printBasicBlockLabel(MO.getMachineBasicBlock());
@ -195,7 +195,7 @@ void X86IntelAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
assert(isMem(MI, Op) && "Invalid memory reference!");
const MachineOperand &BaseReg = MI->getOperand(Op);
int ScaleVal = MI->getOperand(Op+1).getImmedValue();
int ScaleVal = MI->getOperand(Op+1).getImm();
const MachineOperand &IndexReg = MI->getOperand(Op+2);
const MachineOperand &DispSpec = MI->getOperand(Op+3);
@ -220,7 +220,7 @@ void X86IntelAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
O << " + ";
printOp(DispSpec, "mem");
} else {
int DispVal = DispSpec.getImmedValue();
int DispVal = DispSpec.getImm();
if (DispVal || (!BaseReg.getReg() && !IndexReg.getReg())) {
if (NeedPlus)
if (DispVal > 0)