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R600/SI: Emit config values in register value pairs.

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Instead of emitting config values in a predefined order, the code
emitter will now emit a 32-bit register index followed by the 32-bit
config value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179546 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
2013-04-15 17:51:35 +00:00
parent bf1efe6421
commit 9a256300f8
3 changed files with 46 additions and 6 deletions
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11
test/CodeGen/R600/elf.ll
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@@ -1,7 +1,12 @@
; RUN: llc < %s -march=r600 -mcpu=SI -filetype=obj | llvm-readobj -s - | FileCheck %s
; RUN: llc < %s -march=r600 -mcpu=SI -filetype=obj | llvm-readobj -s - | FileCheck --check-prefix=ELF-CHECK %s
; RUN: llc < %s -march=r600 -mcpu=SI -o - | FileCheck --check-prefix=CONFIG-CHECK %s
; CHECK: Format: ELF32
; CHECK: Name: .AMDGPU.config
; ELF-CHECK: Format: ELF32
; ELF-CHECK: Name: .AMDGPU.config
; CONFIG-CHECK: .section .AMDGPU.config
; CONFIG-CHECK-NEXT: .long 45096
; CONFIG-CHECK-NEXT: .long 0
define void @test(i32 %p) {
%i = add i32 %p, 2
%r = bitcast i32 %i to float