From 9a3dc552022e0e034ef34da889f6ceb9de260c96 Mon Sep 17 00:00:00 2001 From: Nate Begeman Date: Fri, 17 Dec 2010 23:12:19 +0000 Subject: [PATCH] Add vector versions of some existing scalar transforms to aid codegen in matching psign & pblend operations to the IR produced by clang/gcc for their C idioms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122105 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Analysis/ValueTracking.cpp | 7 ++++++ .../InstCombine/InstCombineCasts.cpp | 17 ++++++++++++++ test/Transforms/InstCombine/vec_sext.ll | 22 +++++++++++++++++++ 3 files changed, 46 insertions(+) create mode 100644 test/Transforms/InstCombine/vec_sext.ll diff --git a/lib/Analysis/ValueTracking.cpp b/lib/Analysis/ValueTracking.cpp index 75062953cba..f8145cd0e3d 100644 --- a/lib/Analysis/ValueTracking.cpp +++ b/lib/Analysis/ValueTracking.cpp @@ -678,6 +678,13 @@ unsigned llvm::ComputeNumSignBits(Value *V, const TargetData *TD, Tmp += C->getZExtValue(); if (Tmp > TyBits) Tmp = TyBits; } + // vector ashr X, -> adds C sign bits + if (ConstantVector *C = dyn_cast(U->getOperand(1))) { + if (ConstantInt *CI = dyn_cast_or_null(C->getSplatValue())) { + Tmp += CI->getZExtValue(); + if (Tmp > TyBits) Tmp = TyBits; + } + } return Tmp; case Instruction::Shl: if (ConstantInt *C = dyn_cast(U->getOperand(1))) { diff --git a/lib/Transforms/InstCombine/InstCombineCasts.cpp b/lib/Transforms/InstCombine/InstCombineCasts.cpp index 79a9b09c64d..df2abb5cef2 100644 --- a/lib/Transforms/InstCombine/InstCombineCasts.cpp +++ b/lib/Transforms/InstCombine/InstCombineCasts.cpp @@ -1020,6 +1020,23 @@ Instruction *InstCombiner::visitSExt(SExtInst &CI) { } } + // vector (x ashr x, 31 -> all ones if signed + if (const VectorType *VTy = dyn_cast(DestTy)) { + ICmpInst::Predicate Pred; Value *CmpLHS; + if (match(Src, m_ICmp(Pred, m_Value(CmpLHS), m_Zero()))) { + if (Pred == ICmpInst::ICMP_SLT && CmpLHS->getType() == DestTy) { + const Type *EltTy = VTy->getElementType(); + + // splat the shift constant to a cosntant vector + Constant *Sh = ConstantInt::get(EltTy, EltTy->getScalarSizeInBits()-1); + std::vector Elts(VTy->getNumElements(), Sh); + Constant *VSh = ConstantVector::get(Elts); + + Value *In = Builder->CreateAShr(CmpLHS, VSh, CmpLHS->getName()+".lobit"); + return ReplaceInstUsesWith(CI, In); + } + } + } // If the input is a shl/ashr pair of a same constant, then this is a sign // extension from a smaller value. If we could trust arbitrary bitwidth diff --git a/test/Transforms/InstCombine/vec_sext.ll b/test/Transforms/InstCombine/vec_sext.ll new file mode 100644 index 00000000000..d7ab96b9cfd --- /dev/null +++ b/test/Transforms/InstCombine/vec_sext.ll @@ -0,0 +1,22 @@ +; RUN: opt < %s -instcombine -S | FileCheck %s + +define <4 x i32> @psignd_3(<4 x i32> %a, <4 x i32> %b) nounwind ssp { +entry: + %cmp = icmp slt <4 x i32> %b, zeroinitializer + %sext = sext <4 x i1> %cmp to <4 x i32> + %sub = sub nsw <4 x i32> zeroinitializer, %a + %0 = icmp slt <4 x i32> %sext, zeroinitializer + %sext3 = sext <4 x i1> %0 to <4 x i32> + %1 = xor <4 x i32> %sext3, + %2 = and <4 x i32> %a, %1 + %3 = and <4 x i32> %sext3, %sub + %cond = or <4 x i32> %2, %3 + ret <4 x i32> %cond + +; CHECK: ashr <4 x i32> %b, +; CHECK: sub nsw <4 x i32> zeroinitializer, %a +; CHECK: xor <4 x i32> %b.lobit, +; CHECK: and <4 x i32> %a, %0 +; CHECK: and <4 x i32> %b.lobit, %sub +; CHECK: or <4 x i32> %1, %2 +}