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Revert "SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs splitting too."

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Now Hexagon and SystemZ are not happy with it :-(

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193677 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Juergen Ributzka 2013-10-30 06:36:19 +00:00
parent 4eced19c50
commit 9a5df73e32
4 changed files with 9 additions and 87 deletions
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22
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -4346,28 +4346,6 @@ SDValue DAGCombiner::visitVSELECT(SDNode *N) {
} }
} }
// Treat SETCC as a vector mask and promote the result type based on the
// targets expected SETCC result type. This will ensure that SETCC and VSELECT
// are both split by the type legalizer. This is done to prevent the type
// legalizer from unrolling SETCC into scalar comparions.
EVT SelectVT = N->getValueType(0);
EVT MaskVT = getSetCCResultType(SelectVT);
if (N0.getOpcode() == ISD::SETCC && N0.getValueType() != MaskVT) {
SDLoc MaskDL(N0);
// Extend the mask to the desired value type.
ISD::NodeType ExtendCode =
TargetLowering::getExtendForContent(TLI.getBooleanContents(true));
SDValue Mask = DAG.getNode(ExtendCode, MaskDL, MaskVT, N0);
AddToWorkList(Mask.getNode());
SDValue LHS = N->getOperand(1);
SDValue RHS = N->getOperand(2);
return DAG.getNode(ISD::VSELECT, DL, SelectVT, Mask, LHS, RHS);
}
return SDValue(); return SDValue();
} }

21
lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
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@ -492,19 +492,14 @@ void DAGTypeLegalizer::SplitRes_SELECT(SDNode *N, SDValue &Lo,
SDValue Cond = N->getOperand(0); SDValue Cond = N->getOperand(0);
CL = CH = Cond; CL = CH = Cond;
if (Cond.getValueType().isVector()) { if (Cond.getValueType().isVector()) {
if (Cond.getOpcode() == ISD::SETCC) { assert(Cond.getValueType().getVectorElementType() == MVT::i1 &&
assert(Cond.getValueType() == getSetCCResultType(N->getValueType(0)) && "Condition legalized before result?");
"Condition has not been prepared for split!"); unsigned NumElements = Cond.getValueType().getVectorNumElements();
GetSplitVector(Cond, CL, CH); EVT VCondTy = EVT::getVectorVT(*DAG.getContext(), MVT::i1, NumElements / 2);
} else { CL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VCondTy, Cond,
EVT ETy = Cond.getValueType().getVectorElementType(); DAG.getConstant(0, TLI.getVectorIdxTy()));
unsigned NumElements = Cond.getValueType().getVectorNumElements(); CH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VCondTy, Cond,
EVT VCondTy = EVT::getVectorVT(*DAG.getContext(), ETy, NumElements / 2); DAG.getConstant(NumElements / 2, TLI.getVectorIdxTy()));
CL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VCondTy, Cond,
DAG.getConstant(0, TLI.getVectorIdxTy()));
CH = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VCondTy, Cond,
DAG.getConstant(NumElements / 2, TLI.getVectorIdxTy()));
}
} }
Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), CL, LL, RL); Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), CL, LL, RL);

11
lib/Target/X86/X86ISelLowering.cpp
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@ -1546,16 +1546,7 @@ void X86TargetLowering::resetOperationActions() {
} }
EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const { EVT X86TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
if (!VT.isVector()) if (!VT.isVector()) return MVT::i8;
return MVT::i8;
const TargetMachine &TM = getTargetMachine();
if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512())
switch(VT.getVectorNumElements()) {
case 8: return MVT::v8i1;
case 16: return MVT::v16i1;
}
return VT.changeVectorElementTypeToInteger(); return VT.changeVectorElementTypeToInteger();
} }

42
test/CodeGen/X86/vec_split.ll
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@ -1,42 +0,0 @@
; RUN: llc -march=x86-64 -mcpu=corei7 < %s | FileCheck %s -check-prefix=SSE4
; RUN: llc -march=x86-64 -mcpu=corei7-avx < %s | FileCheck %s -check-prefix=AVX1
; RUN: llc -march=x86-64 -mcpu=core-avx2 < %s | FileCheck %s -check-prefix=AVX2
define <16 x i16> @split16(<16 x i16> %a, <16 x i16> %b, <16 x i8> %__mask) {
; SSE4-LABEL: split16:
; SSE4: pminuw
; SSE4: pminuw
; SSE4: ret
; AVX1-LABEL: split16:
; AVX1: vpminuw
; AVX1: vpminuw
; AVX1: ret
; AVX2-LABEL: split16:
; AVX2: vpminuw
; AVX2: ret
%1 = icmp ult <16 x i16> %a, %b
%2 = select <16 x i1> %1, <16 x i16> %a, <16 x i16> %b
ret <16 x i16> %2
}
define <32 x i16> @split32(<32 x i16> %a, <32 x i16> %b, <32 x i8> %__mask) {
; SSE4-LABEL: split32:
; SSE4: pminuw
; SSE4: pminuw
; SSE4: pminuw
; SSE4: pminuw
; SSE4: ret
; AVX1-LABEL: split32:
; AVX1: vpminuw
; AVX1: vpminuw
; AVX1: vpminuw
; AVX1: vpminuw
; AVX1: ret
; AVX2-LABEL: split32:
; AVX2: vpminuw
; AVX2: vpminuw
; AVX2: ret
%1 = icmp ult <32 x i16> %a, %b
%2 = select <32 x i1> %1, <32 x i16> %a, <32 x i16> %b
ret <32 x i16> %2
}