diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index 21943a902d7..a2eb9c7acb9 100644
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -60,6 +60,11 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
   addRegisterClass(MVT::i32, V8::IntRegsRegisterClass);
   addRegisterClass(MVT::f32, V8::FPRegsRegisterClass);
   addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass);
+
+  // Sparc doesn't have sext_inreg, replace them with shl/sra
+  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16  , Expand);
+  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8   , Expand);
+  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1   , Expand);
   
   computeRegisterProperties();
 }
diff --git a/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp b/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
index 21943a902d7..a2eb9c7acb9 100644
--- a/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
+++ b/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
@@ -60,6 +60,11 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
   addRegisterClass(MVT::i32, V8::IntRegsRegisterClass);
   addRegisterClass(MVT::f32, V8::FPRegsRegisterClass);
   addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass);
+
+  // Sparc doesn't have sext_inreg, replace them with shl/sra
+  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16  , Expand);
+  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8   , Expand);
+  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1   , Expand);
   
   computeRegisterProperties();
 }