diff --git a/lib/Target/R600/R600MachineScheduler.cpp b/lib/Target/R600/R600MachineScheduler.cpp index a31168ba677..bcde5fb50da 100644 --- a/lib/Target/R600/R600MachineScheduler.cpp +++ b/lib/Target/R600/R600MachineScheduler.cpp @@ -26,7 +26,7 @@ using namespace llvm; void R600SchedStrategy::initialize(ScheduleDAGMI *dag) { assert(dag->hasVRegLiveness() && "R600SchedStrategy needs vreg liveness"); DAG = static_cast(dag); - const AMDGPUSubtarget &ST = DAG->TM.getSubtarget(); + const AMDGPUSubtarget &ST = DAG->MF.getSubtarget(); TII = static_cast(DAG->TII); TRI = static_cast(DAG->TRI); VLIW5 = !ST.hasCaymanISA(); diff --git a/lib/Target/R600/SIMachineFunctionInfo.cpp b/lib/Target/R600/SIMachineFunctionInfo.cpp index 198dd568374..587ea63d679 100644 --- a/lib/Target/R600/SIMachineFunctionInfo.cpp +++ b/lib/Target/R600/SIMachineFunctionInfo.cpp @@ -39,8 +39,8 @@ SIMachineFunctionInfo::SpilledReg SIMachineFunctionInfo::getSpilledReg( unsigned FrameIndex, unsigned SubIdx) { const MachineFrameInfo *FrameInfo = MF->getFrameInfo(); - const SIRegisterInfo *TRI = static_cast( - MF->getTarget().getSubtarget().getRegisterInfo()); + const SIRegisterInfo *TRI = static_cast( + MF->getSubtarget().getRegisterInfo()); MachineRegisterInfo &MRI = MF->getRegInfo(); int64_t Offset = FrameInfo->getObjectOffset(FrameIndex); Offset += SubIdx * 4; @@ -70,7 +70,7 @@ SIMachineFunctionInfo::SpilledReg SIMachineFunctionInfo::getSpilledReg( unsigned SIMachineFunctionInfo::getMaximumWorkGroupSize( const MachineFunction &MF) const { - const AMDGPUSubtarget &ST = MF.getTarget().getSubtarget(); + const AMDGPUSubtarget &ST = MF.getSubtarget(); // FIXME: We should get this information from kernel attributes if it // is available. return getShaderType() == ShaderType::COMPUTE ? 256 : ST.getWavefrontSize();