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Added the LODS (load byte into register, usually
as part string parsing) instructions to the Intel instruction tables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82089 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1548,6 +1548,10 @@ def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
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"lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
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def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
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"lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
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// String manipulation instructions
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def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", []>;
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//===----------------------------------------------------------------------===//
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// Non-Instruction Patterns
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@ -3684,6 +3684,12 @@ def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
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"lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
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def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
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"lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
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// String manipulation instructions
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def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", []>;
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def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", []>, OpSize;
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def LODSD : I<0xAD, RawFrm, (outs), (ins), "lodsd", []>;
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//===----------------------------------------------------------------------===//
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// Non-Instruction Patterns
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