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[ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205887 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bradley Smith
2014-04-09 14:44:07 +00:00
parent 86c067813c
commit 9a9fa81c1a
2 changed files with 4 additions and 2 deletions
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4
lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
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@@ -2001,7 +2001,7 @@ static DecodeStatus DecodeSIMDLdStSingle(llvm::MCInst &Inst, uint32_t insn,
Inst.addOperand(MCOperand::CreateImm(index));
}
DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
switch (Inst.getOpcode()) {
case ARM64::ST1i8_POST:
@@ -2162,7 +2162,7 @@ static DecodeStatus DecodeSIMDLdStSingleTied(llvm::MCInst &Inst, uint32_t insn,
}
Inst.addOperand(MCOperand::CreateImm(index));
DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
switch (Inst.getOpcode()) {
case ARM64::LD1i8_POST: