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https://github.com/c64scene-ar/llvm-6502.git
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Reduce (cmp 0, and_su (foo, bar)) into (bit foo, bar). This saves extra instruction. Patch inspired by Brian Lucas!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90819 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov
parent
3a41ddb1b9
commit
9aa1ec87b0
@ -92,7 +92,9 @@ def addr : ComplexPattern<iPTR, 2, "SelectAddr", [], []>;
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// Pattern Fragments
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def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>;
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def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 ( extloadi8 node:$ptr))>;
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def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{
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return N->hasOneUse();
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}]>;
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//===----------------------------------------------------------------------===//
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// Instruction list..
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@ -826,6 +828,65 @@ def CMP16mr : Pseudo<(outs), (ins memsrc:$src1, GR16:$src2),
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"cmp.w\t{$src1, $src2}",
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[(MSP430cmp (load addr:$src1), GR16:$src2), (implicit SRW)]>;
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// BIT TESTS, just sets condition codes
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// Note that the C condition is set differently than when using CMP.
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let isCommutable = 1 in {
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def BIT8rr : Pseudo<(outs), (ins GR8:$src1, GR8:$src2),
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"bit.b\t{$src2, $src1}",
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[(MSP430cmp 0, (and_su GR8:$src1, GR8:$src2)),
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(implicit SRW)]>;
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def BIT16rr : Pseudo<(outs), (ins GR16:$src1, GR16:$src2),
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"bit.w\t{$src2, $src1}",
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[(MSP430cmp 0, (and_su GR16:$src1, GR16:$src2)),
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(implicit SRW)]>;
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}
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def BIT8ri : Pseudo<(outs), (ins GR8:$src1, i8imm:$src2),
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"bit.b\t{$src2, $src1}",
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[(MSP430cmp 0, (and_su GR8:$src1, imm:$src2)),
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(implicit SRW)]>;
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def BIT16ri : Pseudo<(outs), (ins GR16:$src1, i16imm:$src2),
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"bit.w\t{$src2, $src1}",
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[(MSP430cmp 0, (and_su GR16:$src1, imm:$src2)),
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(implicit SRW)]>;
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def BIT8rm : Pseudo<(outs), (ins GR8:$src1, memdst:$src2),
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"bit.b\t{$src2, $src1}",
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[(MSP430cmp 0, (and_su GR8:$src1, (load addr:$src2))),
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(implicit SRW)]>;
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def BIT16rm : Pseudo<(outs), (ins GR16:$src1, memdst:$src2),
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"bit.w\t{$src2, $src1}",
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[(MSP430cmp 0, (and_su GR16:$src1, (load addr:$src2))),
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(implicit SRW)]>;
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def BIT8mr : Pseudo<(outs), (ins memsrc:$src1, GR8:$src2),
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"bit.b\t{$src2, $src1}",
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[(MSP430cmp 0, (and_su (load addr:$src1), GR8:$src2)),
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(implicit SRW)]>;
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def BIT16mr : Pseudo<(outs), (ins memsrc:$src1, GR16:$src2),
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"bit.w\t{$src2, $src1}",
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[(MSP430cmp 0, (and_su (load addr:$src1), GR16:$src2)),
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(implicit SRW)]>;
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def BIT8mi : Pseudo<(outs), (ins memsrc:$src1, i8imm:$src2),
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"bit.b\t{$src2, $src1}",
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[(MSP430cmp 0, (and_su (load addr:$src1), (i8 imm:$src2))),
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(implicit SRW)]>;
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def BIT16mi : Pseudo<(outs), (ins memsrc:$src1, i16imm:$src2),
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"bit.w\t{$src2, $src1}",
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[(MSP430cmp 0, (and_su (load addr:$src1), (i16 imm:$src2))),
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(implicit SRW)]>;
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def BIT8mm : Pseudo<(outs), (ins memsrc:$src1, memsrc:$src2),
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"bit.b\t{$src2, $src1}",
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[(MSP430cmp 0, (and_su (i8 (load addr:$src1)),
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(load addr:$src2))),
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(implicit SRW)]>;
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def BIT16mm : Pseudo<(outs), (ins memsrc:$src1, memsrc:$src2),
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"bit.w\t{$src2, $src1}",
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[(MSP430cmp 0, (and_su (i16 (load addr:$src1)),
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(load addr:$src2))),
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(implicit SRW)]>;
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} // Defs = [SRW]
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//===----------------------------------------------------------------------===//
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@ -908,3 +969,6 @@ def : Pat<(store (subc (load addr:$dst), (i8 (load addr:$src))), addr:$dst),
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// peephole patterns
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def : Pat<(and GR16:$src, 255), (ZEXT16r GR16:$src)>;
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def : Pat<(MSP430cmp 0, (trunc (and_su GR16:$src1, GR16:$src2))),
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(BIT8rr (EXTRACT_SUBREG GR16:$src1, subreg_8bit),
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(EXTRACT_SUBREG GR16:$src2, subreg_8bit))>;
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166
test/CodeGen/MSP430/bit.ll
Normal file
166
test/CodeGen/MSP430/bit.ll
Normal file
@ -0,0 +1,166 @@
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; RUN: llvm-as < %s | llc -march=msp430 | FileCheck %s
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target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:32"
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target triple = "msp430-generic-generic"
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@foo8 = external global i8;
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@bar8 = external global i8;
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define i8 @bitbrr(i8 %a, i8 %b) nounwind {
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%t1 = and i8 %a, %b
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%t2 = icmp ne i8 %t1, 0
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%t3 = zext i1 %t2 to i8
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ret i8 %t3
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}
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; CHECK: bitbrr:
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; CHECK: bit.b r14, r15
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define i8 @bitbri(i8 %a) nounwind {
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%t1 = and i8 %a, 15
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%t2 = icmp ne i8 %t1, 0
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%t3 = zext i1 %t2 to i8
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ret i8 %t3
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}
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; CHECK: bitbri:
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; CHECK: bit.b #15, r15
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define i8 @bitbir(i8 %a) nounwind {
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%t1 = and i8 15, %a
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%t2 = icmp ne i8 %t1, 0
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%t3 = zext i1 %t2 to i8
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ret i8 %t3
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}
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; CHECK: bitbir:
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; CHECK: bit.b #15, r15
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define i8 @bitbmi() nounwind {
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%t1 = load i8* @foo8
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%t2 = and i8 %t1, 15
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%t3 = icmp ne i8 %t2, 0
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%t4 = zext i1 %t3 to i8
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ret i8 %t4
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}
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; CHECK: bitbmi:
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; CHECK: bit.b #15, &foo8
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define i8 @bitbim() nounwind {
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%t1 = load i8* @foo8
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%t2 = and i8 15, %t1
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%t3 = icmp ne i8 %t2, 0
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%t4 = zext i1 %t3 to i8
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ret i8 %t4
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}
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; CHECK: bitbim:
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; CHECK: bit.b #15, &foo8
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define i8 @bitbrm(i8 %a) nounwind {
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%t1 = load i8* @foo8
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%t2 = and i8 %a, %t1
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%t3 = icmp ne i8 %t2, 0
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%t4 = zext i1 %t3 to i8
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ret i8 %t4
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}
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; CHECK: bitbrm:
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; CHECK: bit.b &foo8, r15
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define i8 @bitbmr(i8 %a) nounwind {
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%t1 = load i8* @foo8
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%t2 = and i8 %t1, %a
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%t3 = icmp ne i8 %t2, 0
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%t4 = zext i1 %t3 to i8
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ret i8 %t4
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}
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; CHECK: bitbmr:
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; CHECK: bit.b r15, &foo8
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define i8 @bitbmm() nounwind {
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%t1 = load i8* @foo8
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%t2 = load i8* @bar8
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%t3 = and i8 %t1, %t2
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%t4 = icmp ne i8 %t3, 0
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%t5 = zext i1 %t4 to i8
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ret i8 %t5
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}
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; CHECK: bitbmm:
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; CHECK: bit.b &bar8, &foo8
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@foo16 = external global i16;
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@bar16 = external global i16;
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define i16 @bitwrr(i16 %a, i16 %b) nounwind {
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%t1 = and i16 %a, %b
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%t2 = icmp ne i16 %t1, 0
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%t3 = zext i1 %t2 to i16
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ret i16 %t3
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}
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; CHECK: bitwrr:
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; CHECK: bit.w r14, r15
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define i16 @bitwri(i16 %a) nounwind {
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%t1 = and i16 %a, 4080
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%t2 = icmp ne i16 %t1, 0
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%t3 = zext i1 %t2 to i16
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ret i16 %t3
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}
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; CHECK: bitwri:
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; CHECK: bit.w #4080, r15
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define i16 @bitwir(i16 %a) nounwind {
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%t1 = and i16 4080, %a
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%t2 = icmp ne i16 %t1, 0
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%t3 = zext i1 %t2 to i16
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ret i16 %t3
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}
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; CHECK: bitwir:
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; CHECK: bit.w #4080, r15
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define i16 @bitwmi() nounwind {
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%t1 = load i16* @foo16
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%t2 = and i16 %t1, 4080
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%t3 = icmp ne i16 %t2, 0
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%t4 = zext i1 %t3 to i16
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ret i16 %t4
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}
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; CHECK: bitwmi:
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; CHECK: bit.w #4080, &foo16
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define i16 @bitwim() nounwind {
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%t1 = load i16* @foo16
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%t2 = and i16 4080, %t1
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%t3 = icmp ne i16 %t2, 0
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%t4 = zext i1 %t3 to i16
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ret i16 %t4
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}
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; CHECK: bitwim:
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; CHECK: bit.w #4080, &foo16
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define i16 @bitwrm(i16 %a) nounwind {
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%t1 = load i16* @foo16
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%t2 = and i16 %a, %t1
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%t3 = icmp ne i16 %t2, 0
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%t4 = zext i1 %t3 to i16
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ret i16 %t4
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}
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; CHECK: bitwrm:
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; CHECK: bit.w &foo16, r15
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define i16 @bitwmr(i16 %a) nounwind {
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%t1 = load i16* @foo16
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%t2 = and i16 %t1, %a
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%t3 = icmp ne i16 %t2, 0
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%t4 = zext i1 %t3 to i16
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ret i16 %t4
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}
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; CHECK: bitwmr:
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; CHECK: bit.w r15, &foo16
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define i16 @bitwmm() nounwind {
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%t1 = load i16* @foo16
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%t2 = load i16* @bar16
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%t3 = and i16 %t1, %t2
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%t4 = icmp ne i16 %t3, 0
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%t5 = zext i1 %t4 to i16
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ret i16 %t5
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}
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; CHECK: bitwmm:
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; CHECK: bit.w &bar16, &foo16
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