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Move FP_REG_KILL closer to the actual branch instruction.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10563 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Alkis Evlogimenos 2003-12-20 17:28:15 +00:00
parent e0bb3e766d
commit 9abc81790e
2 changed files with 10 additions and 4 deletions
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7
lib/Target/X86/InstSelectSimple.cpp
View File

@ -883,11 +883,12 @@ static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
///
void ISel::visitBranchInst(BranchInst &BI) {
BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
BuildMI(BB, X86::FP_REG_KILL, 0);
if (!BI.isConditional()) { // Unconditional branch?
if (BI.getSuccessor(0) != NextBB)
if (BI.getSuccessor(0) != NextBB) {
BuildMI(BB, X86::FP_REG_KILL, 0);
BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
}
return;
}
@ -898,6 +899,7 @@ void ISel::visitBranchInst(BranchInst &BI) {
// computed some other way...
unsigned condReg = getReg(BI.getCondition());
BuildMI(BB, X86::CMPri8, 2).addReg(condReg).addZImm(0);
BuildMI(BB, X86::FP_REG_KILL, 0);
if (BI.getSuccessor(1) == NextBB) {
if (BI.getSuccessor(0) != NextBB)
BuildMI(BB, X86::JNE, 1).addPCDisp(BI.getSuccessor(0));
@ -936,6 +938,7 @@ void ISel::visitBranchInst(BranchInst &BI) {
X86::JS, X86::JNS },
};
BuildMI(BB, X86::FP_REG_KILL, 0);
if (BI.getSuccessor(0) != NextBB) {
BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(0));
if (BI.getSuccessor(1) != NextBB)

7
lib/Target/X86/X86ISelSimple.cpp
View File

@ -883,11 +883,12 @@ static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
///
void ISel::visitBranchInst(BranchInst &BI) {
BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
BuildMI(BB, X86::FP_REG_KILL, 0);
if (!BI.isConditional()) { // Unconditional branch?
if (BI.getSuccessor(0) != NextBB)
if (BI.getSuccessor(0) != NextBB) {
BuildMI(BB, X86::FP_REG_KILL, 0);
BuildMI(BB, X86::JMP, 1).addPCDisp(BI.getSuccessor(0));
}
return;
}
@ -898,6 +899,7 @@ void ISel::visitBranchInst(BranchInst &BI) {
// computed some other way...
unsigned condReg = getReg(BI.getCondition());
BuildMI(BB, X86::CMPri8, 2).addReg(condReg).addZImm(0);
BuildMI(BB, X86::FP_REG_KILL, 0);
if (BI.getSuccessor(1) == NextBB) {
if (BI.getSuccessor(0) != NextBB)
BuildMI(BB, X86::JNE, 1).addPCDisp(BI.getSuccessor(0));
@ -936,6 +938,7 @@ void ISel::visitBranchInst(BranchInst &BI) {
X86::JS, X86::JNS },
};
BuildMI(BB, X86::FP_REG_KILL, 0);
if (BI.getSuccessor(0) != NextBB) {
BuildMI(BB, OpcodeTab[isSigned][OpNum], 1).addPCDisp(BI.getSuccessor(0));
if (BI.getSuccessor(1) != NextBB)