6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-08-25 16:29:20 +00:00
Code Issues Projects Releases Wiki Activity

Simplify condition checking as CONCAT assume all inputs of the same type.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166260 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Michael Liao 2012-10-19 03:17:00 +00:00
parent 89e7b356f2
commit 9aecdb51c7
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -8629,9 +8629,9 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
// (extract_subvec (concat V1, V2, ...), i)
// Into:
// Vi if possible
for (unsigned i = 0, e = V->getNumOperands(); i != e; ++i)
if (V->getOperand(i).getValueType() != NVT)
return SDValue();
// Only operand 0 is checked as 'concat' assumes all inputs of the same type.
if (V->getOperand(0).getValueType() != NVT)
return SDValue();
unsigned Idx = dyn_cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
unsigned NumElems = NVT.getVectorNumElements();
assert((Idx % NumElems) == 0 &&