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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-21 18:29:46 +00:00
R600/SI: Only create one instruction when spilling/restoring register v3
The register spiller assumes that only one new instruction is created when spilling and restoring registers, so we need to emit pseudo instructions for vector register spills and lower them after register allocation. v2: - Fix calculation of lane index - Extend VGPR liveness to end of program. v3: - Use SIMM16 field of S_NOP to specify multiple NOPs. https://bugs.freedesktop.org/show_bug.cgi?id=75005 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207843 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
parent
ecc1896600
commit
9b22626068
@ -187,27 +187,45 @@ void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
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SIMachineFunctionInfo *MFI = MBB.getParent()->getInfo<SIMachineFunctionInfo>();
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DebugLoc DL = MBB.findDebugLoc(MI);
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unsigned KillFlag = isKill ? RegState::Kill : 0;
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MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
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if (TRI->getCommonSubClass(RC, &AMDGPU::SGPR_32RegClass)) {
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unsigned Lane = MFI->SpillTracker.getNextLane(MRI);
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BuildMI(MBB, MI, DL, get(AMDGPU::V_WRITELANE_B32),
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MFI->SpillTracker.LaneVGPR)
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unsigned Lane = MFI->SpillTracker.reserveLanes(MRI, MBB.getParent());
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BuildMI(MBB, MI, DL, get(AMDGPU::V_WRITELANE_B32), MFI->SpillTracker.LaneVGPR)
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.addReg(SrcReg, KillFlag)
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.addImm(Lane);
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MFI->SpillTracker.addSpilledReg(FrameIndex, MFI->SpillTracker.LaneVGPR, Lane);
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} else if (RI.isSGPRClass(RC)) {
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// We are only allowed to create one new instruction when spilling
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// registers, so we need to use pseudo instruction for vector
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// registers.
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//
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// Reserve a spot in the spill tracker for each sub-register of
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// the vector register.
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unsigned NumSubRegs = RC->getSize() / 4;
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unsigned FirstLane = MFI->SpillTracker.reserveLanes(MRI, MBB.getParent(),
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NumSubRegs);
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MFI->SpillTracker.addSpilledReg(FrameIndex, MFI->SpillTracker.LaneVGPR,
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Lane);
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} else {
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for (unsigned i = 0, e = RC->getSize() / 4; i != e; ++i) {
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unsigned SubReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
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BuildMI(MBB, MI, MBB.findDebugLoc(MI), get(AMDGPU::COPY), SubReg)
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.addReg(SrcReg, 0, RI.getSubRegFromChannel(i));
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storeRegToStackSlot(MBB, MI, SubReg, isKill, FrameIndex + i,
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&AMDGPU::SReg_32RegClass, TRI);
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FirstLane);
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unsigned Opcode;
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switch (RC->getSize() * 8) {
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case 64: Opcode = AMDGPU::SI_SPILL_S64_SAVE; break;
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case 128: Opcode = AMDGPU::SI_SPILL_S128_SAVE; break;
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case 256: Opcode = AMDGPU::SI_SPILL_S256_SAVE; break;
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case 512: Opcode = AMDGPU::SI_SPILL_S512_SAVE; break;
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default: llvm_unreachable("Cannot spill register class");
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}
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BuildMI(MBB, MI, DL, get(Opcode), MFI->SpillTracker.LaneVGPR)
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.addReg(SrcReg)
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.addImm(FrameIndex);
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} else {
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llvm_unreachable("VGPR spilling not supported");
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}
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}
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@ -216,32 +234,127 @@ void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
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SIMachineFunctionInfo *MFI = MBB.getParent()->getInfo<SIMachineFunctionInfo>();
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DebugLoc DL = MBB.findDebugLoc(MI);
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if (TRI->getCommonSubClass(RC, &AMDGPU::SReg_32RegClass)) {
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SIMachineFunctionInfo::SpilledReg Spill =
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SIMachineFunctionInfo::SpilledReg Spill =
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MFI->SpillTracker.getSpilledReg(FrameIndex);
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assert(Spill.VGPR);
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BuildMI(MBB, MI, DL, get(AMDGPU::V_READLANE_B32), DestReg)
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.addReg(Spill.VGPR)
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.addImm(Spill.Lane);
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} else {
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for (unsigned i = 0, e = RC->getSize() / 4; i != e; ++i) {
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unsigned Flags = RegState::Define;
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if (i == 0) {
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Flags |= RegState::Undef;
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}
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unsigned SubReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
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loadRegFromStackSlot(MBB, MI, SubReg, FrameIndex + i,
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&AMDGPU::SReg_32RegClass, TRI);
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BuildMI(MBB, MI, DL, get(AMDGPU::COPY))
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.addReg(DestReg, Flags, RI.getSubRegFromChannel(i))
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.addReg(SubReg);
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insertNOPs(MI, 3);
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} else if (RI.isSGPRClass(RC)){
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unsigned Opcode;
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switch(RC->getSize() * 8) {
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case 64: Opcode = AMDGPU::SI_SPILL_S64_RESTORE; break;
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case 128: Opcode = AMDGPU::SI_SPILL_S128_RESTORE; break;
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case 256: Opcode = AMDGPU::SI_SPILL_S256_RESTORE; break;
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case 512: Opcode = AMDGPU::SI_SPILL_S512_RESTORE; break;
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default: llvm_unreachable("Cannot spill register class");
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}
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SIMachineFunctionInfo::SpilledReg Spill =
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MFI->SpillTracker.getSpilledReg(FrameIndex);
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BuildMI(MBB, MI, DL, get(Opcode), DestReg)
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.addReg(Spill.VGPR)
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.addImm(FrameIndex);
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insertNOPs(MI, 3);
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} else {
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llvm_unreachable("VGPR spilling not supported");
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}
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}
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static unsigned getNumSubRegsForSpillOp(unsigned Op) {
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switch (Op) {
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case AMDGPU::SI_SPILL_S512_SAVE:
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case AMDGPU::SI_SPILL_S512_RESTORE:
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return 16;
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case AMDGPU::SI_SPILL_S256_SAVE:
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case AMDGPU::SI_SPILL_S256_RESTORE:
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return 8;
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case AMDGPU::SI_SPILL_S128_SAVE:
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case AMDGPU::SI_SPILL_S128_RESTORE:
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return 4;
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case AMDGPU::SI_SPILL_S64_SAVE:
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case AMDGPU::SI_SPILL_S64_RESTORE:
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return 2;
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default: llvm_unreachable("Invalid spill opcode");
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}
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}
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void SIInstrInfo::insertNOPs(MachineBasicBlock::iterator MI,
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int Count) const {
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while (Count > 0) {
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int Arg;
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if (Count >= 8)
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Arg = 7;
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else
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Arg = Count - 1;
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Count -= 8;
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BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(AMDGPU::S_NOP))
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.addImm(Arg);
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}
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}
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bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
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SIMachineFunctionInfo *MFI =
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MI->getParent()->getParent()->getInfo<SIMachineFunctionInfo>();
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MachineBasicBlock &MBB = *MI->getParent();
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DebugLoc DL = MBB.findDebugLoc(MI);
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switch (MI->getOpcode()) {
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default: return AMDGPUInstrInfo::expandPostRAPseudo(MI);
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// SGPR register spill
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case AMDGPU::SI_SPILL_S512_SAVE:
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case AMDGPU::SI_SPILL_S256_SAVE:
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case AMDGPU::SI_SPILL_S128_SAVE:
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case AMDGPU::SI_SPILL_S64_SAVE: {
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unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
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unsigned FrameIndex = MI->getOperand(2).getImm();
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for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
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SIMachineFunctionInfo::SpilledReg Spill;
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unsigned SubReg = RI.getPhysRegSubReg(MI->getOperand(1).getReg(),
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&AMDGPU::SGPR_32RegClass, i);
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Spill = MFI->SpillTracker.getSpilledReg(FrameIndex);
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BuildMI(MBB, MI, DL, get(AMDGPU::V_WRITELANE_B32),
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MI->getOperand(0).getReg())
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.addReg(SubReg)
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.addImm(Spill.Lane + i);
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}
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MI->eraseFromParent();
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break;
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}
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// SGPR register restore
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case AMDGPU::SI_SPILL_S512_RESTORE:
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case AMDGPU::SI_SPILL_S256_RESTORE:
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case AMDGPU::SI_SPILL_S128_RESTORE:
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case AMDGPU::SI_SPILL_S64_RESTORE: {
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unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
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for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
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SIMachineFunctionInfo::SpilledReg Spill;
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unsigned FrameIndex = MI->getOperand(2).getImm();
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unsigned SubReg = RI.getPhysRegSubReg(MI->getOperand(0).getReg(),
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&AMDGPU::SGPR_32RegClass, i);
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Spill = MFI->SpillTracker.getSpilledReg(FrameIndex);
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BuildMI(MBB, MI, DL, get(AMDGPU::V_READLANE_B32), SubReg)
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.addReg(MI->getOperand(1).getReg())
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.addImm(Spill.Lane + i);
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}
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MI->eraseFromParent();
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break;
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}
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}
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return true;
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}
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MachineInstr *SIInstrInfo::commuteInstruction(MachineInstr *MI,
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bool NewMI) const {
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@ -73,6 +73,8 @@ public:
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
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unsigned commuteOpcode(unsigned Opcode) const;
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MachineInstr *commuteInstruction(MachineInstr *MI,
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@ -165,6 +167,8 @@ public:
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void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I,
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unsigned SavReg, unsigned IndexReg) const;
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void insertNOPs(MachineBasicBlock::iterator MI, int Count) const;
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};
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namespace AMDGPU {
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@ -369,7 +369,7 @@ def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "S_GETREG_REGRD_B32", []>;
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let Predicates = [isSI] in {
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//def S_NOP : SOPP_ <0x00000000, "S_NOP", []>;
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def S_NOP : SOPP <0x00000000, (ins i16imm:$SIMM16), "S_NOP $SIMM16", []>;
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let isTerminator = 1 in {
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@ -1574,6 +1574,27 @@ def V_SUB_F64 : InstSI <
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} // end usesCustomInserter
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multiclass SI_SPILL_SGPR <RegisterClass sgpr_class> {
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def _SAVE : InstSI <
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(outs VReg_32:$dst),
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(ins sgpr_class:$src, i32imm:$frame_idx),
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"", []
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>;
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def _RESTORE : InstSI <
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(outs sgpr_class:$dst),
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(ins VReg_32:$src, i32imm:$frame_idx),
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"", []
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>;
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}
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defm SI_SPILL_S64 : SI_SPILL_SGPR <SReg_64>;
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defm SI_SPILL_S128 : SI_SPILL_SGPR <SReg_128>;
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defm SI_SPILL_S256 : SI_SPILL_SGPR <SReg_256>;
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defm SI_SPILL_S512 : SI_SPILL_SGPR <SReg_512>;
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} // end IsCodeGenOnly, isPseudo
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def : Pat<
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@ -10,8 +10,11 @@
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#include "SIMachineFunctionInfo.h"
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#include "SIInstrInfo.h"
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#include "SIRegisterInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/LLVMContext.h"
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#define MAX_LANES 64
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@ -26,21 +29,57 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
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PSInputAddr(0),
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SpillTracker() { }
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static unsigned createLaneVGPR(MachineRegisterInfo &MRI) {
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return MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
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}
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static unsigned createLaneVGPR(MachineRegisterInfo &MRI, MachineFunction *MF) {
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unsigned VGPR = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
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unsigned SIMachineFunctionInfo::RegSpillTracker::getNextLane(MachineRegisterInfo &MRI) {
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if (!LaneVGPR) {
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LaneVGPR = createLaneVGPR(MRI);
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} else {
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CurrentLane++;
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if (CurrentLane == MAX_LANES) {
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CurrentLane = 0;
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LaneVGPR = createLaneVGPR(MRI);
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// We need to add this register as live out for the function, in order to
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// have the live range calculated directly.
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//
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// When register spilling begins, we have already calculated the live
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// live intervals for all the registers. Since we are spilling SGPRs to
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// VGPRs, we need to update the Lane VGPR's live interval every time we
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// spill or restore a register.
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//
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// Unfortunately, there is no good way to update the live interval as
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// the TargetInstrInfo callbacks for spilling and restoring don't give
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// us access to the live interval information.
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//
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// We are lucky, though, because the InlineSpiller calls
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// LiveRangeEdit::calculateRegClassAndHint() which iterates through
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// all the new register that have been created when restoring a register
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// and calls LiveIntervals::getInterval(), which creates and computes
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// the live interval for the newly created register. However, once this
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// live intervals is created, it doesn't change and since we usually reuse
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// the Lane VGPR multiple times, this means any uses after the first aren't
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// added to the live interval.
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//
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// To work around this, we add Lane VGPRs to the functions live out list,
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// so that we can guarantee its live range will cover all of its uses.
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for (MachineBasicBlock &MBB : *MF) {
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if (MBB.back().getOpcode() == AMDGPU::S_ENDPGM) {
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MBB.back().addOperand(*MF, MachineOperand::CreateReg(VGPR, false, true));
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return VGPR;
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}
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}
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return CurrentLane;
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MF->getFunction()->getContext().emitError(
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"Could not found S_ENGPGM instrtuction.");
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return VGPR;
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}
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unsigned SIMachineFunctionInfo::RegSpillTracker::reserveLanes(
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MachineRegisterInfo &MRI, MachineFunction *MF, unsigned NumRegs) {
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unsigned StartLane = CurrentLane;
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CurrentLane += NumRegs;
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if (!LaneVGPR) {
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LaneVGPR = createLaneVGPR(MRI, MF);
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} else {
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if (CurrentLane >= MAX_LANES) {
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StartLane = CurrentLane = 0;
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LaneVGPR = createLaneVGPR(MRI, MF);
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}
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}
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return StartLane;
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}
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void SIMachineFunctionInfo::RegSpillTracker::addSpilledReg(unsigned FrameIndex,
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@ -43,7 +43,12 @@ public:
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public:
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unsigned LaneVGPR;
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RegSpillTracker() : CurrentLane(0), SpilledRegisters(), LaneVGPR(0) { }
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unsigned getNextLane(MachineRegisterInfo &MRI);
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/// \p NumRegs The number of consecutive registers what need to be spilled.
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/// This function will ensure that all registers are stored in
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/// the same VGPR.
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/// \returns The lane to be used for storing the first register.
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unsigned reserveLanes(MachineRegisterInfo &MRI, MachineFunction *MF,
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unsigned NumRegs = 1);
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void addSpilledReg(unsigned FrameIndex, unsigned Reg, int Lane = -1);
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const SpilledReg& getSpilledReg(unsigned FrameIndex);
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bool programSpillsRegisters() { return !SpilledRegisters.empty(); }
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@ -129,3 +129,10 @@ const TargetRegisterClass *SIRegisterInfo::getSubRegClass(
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return &AMDGPU::VGPR_32RegClass;
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}
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}
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unsigned SIRegisterInfo::getPhysRegSubReg(unsigned Reg,
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const TargetRegisterClass *SubRC,
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unsigned Channel) const {
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unsigned Index = getHWRegIndex(Reg);
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return SubRC->getRegister(Index + Channel);
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}
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@ -63,6 +63,12 @@ struct SIRegisterInfo : public AMDGPURegisterInfo {
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/// be returned.
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const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
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unsigned SubIdx) const;
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/// \p Channel This is the register channel (e.g. a value from 0-16), not the
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/// SubReg index.
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/// \returns The sub-register of Reg that is in Channel.
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unsigned getPhysRegSubReg(unsigned Reg, const TargetRegisterClass *SubRC,
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unsigned Channel) const;
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};
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} // End namespace llvm
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