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R600/SI: Enable named operand table for SALU instructions

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218358 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2014-09-24 02:17:06 +00:00
parent 5f671bae7c
commit 9b50273e54
1 changed files with 8 additions and 0 deletions
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8
lib/Target/R600/SIInstrFormats.td
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@ -164,6 +164,8 @@ class SOP2 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
let mayStore = 0;
let hasSideEffects = 0;
let SALU = 1;
let UseNamedOperandTable = 1;
}
class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
@ -174,6 +176,8 @@ class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
let mayStore = 0;
let hasSideEffects = 0;
let SALU = 1;
let UseNamedOperandTable = 1;
}
class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
@ -183,6 +187,8 @@ class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
let mayStore = 0;
let hasSideEffects = 0;
let SALU = 1;
let UseNamedOperandTable = 1;
}
class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> :
@ -192,6 +198,8 @@ class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> :
let mayStore = 0;
let hasSideEffects = 0;
let SALU = 1;
let UseNamedOperandTable = 1;
}
class SMRD <bits<5> op, bits<1> imm, dag outs, dag ins, string asm,