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Change the scheduler accessor methods to accept an explicit TargetMachine

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argument instead of taking the SelectionDAG's TargetMachine. This is
needed for some upcoming scheduler changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59055 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2008-11-11 17:50:47 +00:00
parent 86d77337fc
commit 9b75b37375
7 changed files with 27 additions and 15 deletions
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10
include/llvm/CodeGen/LinkAllCodegenComponents.h
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@ -42,11 +42,11 @@ namespace {
llvm::linkOcamlGC();
llvm::linkShadowStackGC();
(void) llvm::createBURRListDAGScheduler(NULL, NULL, NULL, false);
(void) llvm::createTDRRListDAGScheduler(NULL, NULL, NULL, false);
(void) llvm::createTDListDAGScheduler(NULL, NULL, NULL, false);
(void) llvm::createFastDAGScheduler(NULL, NULL, NULL, false);
(void) llvm::createDefaultScheduler(NULL, NULL, NULL, false);
(void) llvm::createBURRListDAGScheduler(NULL, NULL, NULL, NULL, false);
(void) llvm::createTDRRListDAGScheduler(NULL, NULL, NULL, NULL, false);
(void) llvm::createTDListDAGScheduler(NULL, NULL, NULL, NULL, false);
(void) llvm::createFastDAGScheduler(NULL, NULL, NULL, NULL, false);
(void) llvm::createDefaultScheduler(NULL, NULL, NULL, NULL, false);
}
} ForceCodegenLinking; // Force link by creating a global definition.

5
include/llvm/CodeGen/ScheduleDAG.h
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@ -395,6 +395,7 @@ namespace llvm {
/// reduction list scheduler.
ScheduleDAG* createBURRListDAGScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
const TargetMachine *TM,
MachineBasicBlock *BB,
bool Fast);
@ -402,6 +403,7 @@ namespace llvm {
/// reduction list scheduler.
ScheduleDAG* createTDRRListDAGScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
const TargetMachine *TM,
MachineBasicBlock *BB,
bool Fast);
@ -409,6 +411,7 @@ namespace llvm {
/// a hazard recognizer.
ScheduleDAG* createTDListDAGScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
const TargetMachine *TM,
MachineBasicBlock *BB,
bool Fast);
@ -416,6 +419,7 @@ namespace llvm {
///
ScheduleDAG *createFastDAGScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
const TargetMachine *TM,
MachineBasicBlock *BB,
bool Fast);
@ -423,6 +427,7 @@ namespace llvm {
/// for the target.
ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
const TargetMachine *TM,
MachineBasicBlock *BB,
bool Fast);

1
include/llvm/CodeGen/SchedulerRegistry.h
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@ -35,6 +35,7 @@ class RegisterScheduler : public MachinePassRegistryNode {
public:
typedef ScheduleDAG *(*FunctionPassCtor)(SelectionDAGISel*, SelectionDAG*,
const TargetMachine *,
MachineBasicBlock*, bool);
static MachinePassRegistry Registry;

3
lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
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@ -652,6 +652,7 @@ void ScheduleDAGFast::ListScheduleBottomUp() {
llvm::ScheduleDAG* llvm::createFastDAGScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
const TargetMachine *TM,
MachineBasicBlock *BB, bool) {
return new ScheduleDAGFast(*DAG, BB, DAG->getTarget());
return new ScheduleDAGFast(*DAG, BB, *TM);
}

3
lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
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@ -541,8 +541,9 @@ void LatencyPriorityQueue::AdjustPriorityOfUnscheduledPreds(SUnit *SU) {
/// recognizer and deletes it when done.
ScheduleDAG* llvm::createTDListDAGScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
const TargetMachine *TM,
MachineBasicBlock *BB, bool Fast) {
return new ScheduleDAGList(*DAG, BB, DAG->getTarget(),
return new ScheduleDAGList(*DAG, BB, *TM,
new LatencyPriorityQueue(),
IS->CreateTargetHazardRecognizer());
}

12
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
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@ -1881,27 +1881,29 @@ void TDRegReductionPriorityQueue::CalculateSethiUllmanNumbers() {
llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
const TargetMachine *TM,
MachineBasicBlock *BB,
bool Fast) {
if (Fast)
return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), true, true,
return new ScheduleDAGRRList(*DAG, BB, *TM, true, true,
new BURegReductionFastPriorityQueue());
const TargetInstrInfo *TII = DAG->getTarget().getInstrInfo();
const TargetRegisterInfo *TRI = DAG->getTarget().getRegisterInfo();
const TargetInstrInfo *TII = TM->getInstrInfo();
const TargetRegisterInfo *TRI = TM->getRegisterInfo();
BURegReductionPriorityQueue *PQ = new BURegReductionPriorityQueue(TII, TRI);
ScheduleDAGRRList *SD =
new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(),true,false, PQ);
new ScheduleDAGRRList(*DAG, BB, *TM, true, false, PQ);
PQ->setScheduleDAG(SD);
return SD;
}
llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
const TargetMachine *TM,
MachineBasicBlock *BB,
bool Fast) {
return new ScheduleDAGRRList(*DAG, BB, DAG->getTarget(), false, Fast,
return new ScheduleDAGRRList(*DAG, BB, *TM, false, Fast,
new TDRegReductionPriorityQueue());
}

8
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
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@ -133,16 +133,17 @@ namespace llvm {
/// for the target.
ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
const TargetMachine *TM,
MachineBasicBlock *BB,
bool Fast) {
TargetLowering &TLI = IS->getTargetLowering();
if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
return createTDListDAGScheduler(IS, DAG, BB, Fast);
return createTDListDAGScheduler(IS, DAG, TM, BB, Fast);
} else {
assert(TLI.getSchedulingPreference() ==
TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
return createBURRListDAGScheduler(IS, DAG, BB, Fast);
return createBURRListDAGScheduler(IS, DAG, TM, BB, Fast);
}
}
}
@ -1053,7 +1054,8 @@ ScheduleDAG *SelectionDAGISel::Schedule() {
RegisterScheduler::setDefault(Ctor);
}
ScheduleDAG *Scheduler = Ctor(this, CurDAG, BB, Fast);
TargetMachine &TM = getTargetLowering().getTargetMachine();
ScheduleDAG *Scheduler = Ctor(this, CurDAG, &TM, BB, Fast);
Scheduler->Run();
return Scheduler;