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Tighten a ARM dag combine condition to avoid an identity transformation, which

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ends up introducing a cycle in the DAG.

rdar://10196296


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140733 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2011-09-28 23:16:31 +00:00
parent d42ca4607b
commit 9b88d2d782
2 changed files with 31 additions and 1 deletions
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2
lib/Target/ARM/ARMISelLowering.cpp
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@ -7344,7 +7344,7 @@ ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
// movne r0, y
/// FIXME: Turn this into a target neutral optimization?
SDValue Res;
if (CC == ARMCC::NE && FalseVal == RHS) {
if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) {
Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc,
N->getOperand(3), Cmp);
} else if (CC == ARMCC::EQ && TrueVal == RHS) {

30
test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll Normal file
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@ -0,0 +1,30 @@
; RUN: llc -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 < %s
; rdar://10196296
; ARM target specific dag combine created a cycle in DAG.
define void @t() nounwind ssp {
%1 = load i64* undef, align 4
%2 = shl i32 5, 0
%3 = zext i32 %2 to i64
%4 = and i64 %1, %3
%5 = lshr i64 %4, undef
switch i64 %5, label %8 [
i64 0, label %9
i64 1, label %6
i64 4, label %9
i64 5, label %7
]
; <label>:6 ; preds = %0
unreachable
; <label>:7 ; preds = %0
unreachable
; <label>:8 ; preds = %0
unreachable
; <label>:9 ; preds = %0, %0
ret void
}