diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 10baccbdf99..723c512c92e 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -3287,7 +3287,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
       case ISD::MUL:
         if (VT == MVT::i32)
           LC = RTLIB::MUL_I32;
-	else if (VT == MVT::i64)
+        else if (VT == MVT::i64)
           LC = RTLIB::MUL_I64;
         break;
       case ISD::FPOW:
diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h
index 558b119954b..c8dc30a4f9c 100644
--- a/lib/Target/X86/X86ISelLowering.h
+++ b/lib/Target/X86/X86ISelLowering.h
@@ -185,7 +185,7 @@ namespace llvm {
       /// in order to obtain suitable precision.
       FRSQRT, FRCP,
 
-      // TLSADDR, THREAThread - Thread Local Storage.
+      // TLSADDR, THREAD_POINTER - Thread Local Storage.
       TLSADDR, THREAD_POINTER,
 
       // EH_RETURN - Exception Handling helpers.