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[FastISel][AArch64] Optimize select when one of the operands is a 'true' or 'false' value.
Optimize selects of i1 in the presence of 'true' and 'false' operands to simple logic operations. This fixes rdar://problem/18960150. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221848 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -150,6 +150,7 @@ private:
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bool foldXALUIntrinsic(AArch64CC::CondCode &CC, const Instruction *I,
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const Value *Cond);
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bool optimizeIntExtLoad(const Instruction *I, MVT RetVT, MVT SrcVT);
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bool optimizeSelect(const SelectInst *SI);
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// Emit helper routines.
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unsigned emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
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@ -2496,6 +2497,63 @@ bool AArch64FastISel::selectCmp(const Instruction *I) {
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return true;
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}
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/// \brief Optimize selects of i1 if one of the operands has a 'true' or 'false'
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/// value.
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bool AArch64FastISel::optimizeSelect(const SelectInst *SI) {
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if (!SI->getType()->isIntegerTy(1))
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return false;
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const Value *Src1Val, *Src2Val;
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unsigned Opc = 0;
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bool NeedExtraOp = false;
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if (auto *CI = dyn_cast<ConstantInt>(SI->getTrueValue())) {
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if (CI->isOne()) {
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Src1Val = SI->getCondition();
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Src2Val = SI->getFalseValue();
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Opc = AArch64::ORRWrr;
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} else {
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assert(CI->isZero());
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Src1Val = SI->getFalseValue();
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Src2Val = SI->getCondition();
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Opc = AArch64::BICWrr;
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}
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} else if (auto *CI = dyn_cast<ConstantInt>(SI->getFalseValue())) {
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if (CI->isOne()) {
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Src1Val = SI->getCondition();
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Src2Val = SI->getTrueValue();
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Opc = AArch64::ORRWrr;
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NeedExtraOp = true;
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} else {
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assert(CI->isZero());
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Src1Val = SI->getCondition();
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Src2Val = SI->getTrueValue();
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Opc = AArch64::ANDWrr;
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}
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}
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if (!Opc)
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return false;
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unsigned Src1Reg = getRegForValue(Src1Val);
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if (!Src1Reg)
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return false;
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bool Src1IsKill = hasTrivialKill(Src1Val);
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unsigned Src2Reg = getRegForValue(Src2Val);
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if (!Src2Reg)
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return false;
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bool Src2IsKill = hasTrivialKill(Src2Val);
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if (NeedExtraOp) {
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Src1Reg = emitLogicalOp_ri(ISD::XOR, MVT::i32, Src1Reg, Src1IsKill, 1);
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Src1IsKill = true;
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}
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unsigned ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32spRegClass, Src1Reg,
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Src1IsKill, Src2Reg, Src2IsKill);
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updateValueMap(SI, ResultReg);
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return true;
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}
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bool AArch64FastISel::selectSelect(const Instruction *I) {
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assert(isa<SelectInst>(I) && "Expected a select instruction.");
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MVT VT;
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@ -2533,6 +2591,9 @@ bool AArch64FastISel::selectSelect(const Instruction *I) {
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AArch64CC::CondCode CC = AArch64CC::NE;
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AArch64CC::CondCode ExtraCC = AArch64CC::AL;
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if (optimizeSelect(SI))
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return true;
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// Try to pickup the flags, so we don't have to emit another compare.
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if (foldXALUIntrinsic(CC, I, Cond)) {
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// Fake request the condition to force emission of the XALU intrinsic.
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@ -284,3 +284,33 @@ define float @select_icmp_sle(i32 %x, i32 %y, float %a, float %b) {
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%2 = select i1 %1, float %a, float %b
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ret float %2
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}
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; Test peephole optimizations for select.
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define zeroext i1 @select_opt1(i1 zeroext %c, i1 zeroext %a) {
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; CHECK-LABEL: select_opt1
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; CHECK: orr {{w[0-9]+}}, w0, w1
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%1 = select i1 %c, i1 true, i1 %a
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ret i1 %1
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}
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define zeroext i1 @select_opt2(i1 zeroext %c, i1 zeroext %a) {
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; CHECK-LABEL: select_opt2
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; CHECK: eor [[REG:w[0-9]+]], w0, #0x1
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; CHECK: orr {{w[0-9]+}}, [[REG]], w1
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%1 = select i1 %c, i1 %a, i1 true
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ret i1 %1
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}
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define zeroext i1 @select_opt3(i1 zeroext %c, i1 zeroext %a) {
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; CHECK-LABEL: select_opt3
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; CHECK: bic {{w[0-9]+}}, w1, w0
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%1 = select i1 %c, i1 false, i1 %a
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ret i1 %1
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}
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define zeroext i1 @select_opt4(i1 zeroext %c, i1 zeroext %a) {
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; CHECK-LABEL: select_opt4
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; CHECK: and {{w[0-9]+}}, w0, w1
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%1 = select i1 %c, i1 %a, i1 false
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ret i1 %1
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}
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