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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-17 05:29:24 +00:00
Adjust to new TargetMachine interface
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13956 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -122,7 +122,7 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
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// perform a final pass over the instructions and compute spill
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// weights, coalesce virtual registers and remove identity moves
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const LoopInfo& loopInfo = getAnalysis<LoopInfo>();
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const TargetInstrInfo& tii = tm_->getInstrInfo();
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const TargetInstrInfo& tii = *tm_->getInstrInfo();
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for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
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mbbi != mbbe; ++mbbi) {
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@ -424,7 +424,7 @@ void LiveIntervals::computeIntervals()
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for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
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mi != miEnd; ++mi) {
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const TargetInstrDescriptor& tid =
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tm_->getInstrInfo().get(mi->getOpcode());
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tm_->getInstrInfo()->get(mi->getOpcode());
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DEBUG(std::cerr << getInstructionIndex(mi) << "\t";
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mi->print(std::cerr, *tm_));
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@ -455,7 +455,7 @@ void LiveIntervals::joinIntervals()
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{
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DEBUG(std::cerr << "********** JOINING INTERVALS ***********\n");
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const TargetInstrInfo& tii = tm_->getInstrInfo();
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const TargetInstrInfo& tii = *tm_->getInstrInfo();
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for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
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mbbi != mbbe; ++mbbi) {
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@ -464,8 +464,7 @@ void LiveIntervals::joinIntervals()
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for (MachineBasicBlock::iterator mi = mbb->begin(), mie = mbb->end();
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mi != mie; ++mi) {
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const TargetInstrDescriptor& tid =
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tm_->getInstrInfo().get(mi->getOpcode());
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const TargetInstrDescriptor& tid = tii.get(mi->getOpcode());
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DEBUG(std::cerr << getInstructionIndex(mi) << '\t';
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mi->print(std::cerr, *tm_););
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@ -159,7 +159,7 @@ void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
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}
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bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
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const TargetInstrInfo &TII = MF.getTarget().getInstrInfo();
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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RegInfo = MF.getTarget().getRegisterInfo();
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assert(RegInfo && "Target doesn't have register information?");
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@ -81,7 +81,7 @@ void ilist_traits<MachineInstr>::transferNodesFromList(
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MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator()
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{
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const TargetInstrInfo& TII = getParent()->getTarget().getInstrInfo();
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const TargetInstrInfo& TII = *getParent()->getTarget().getInstrInfo();
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iterator I = end();
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while (I != begin() && TII.isTerminatorInstr((--I)->getOpcode()));
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if (I != end() && !TII.isTerminatorInstr(I->getOpcode())) ++I;
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@ -322,7 +322,7 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const {
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OS << " = ";
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++StartOp; // Don't print this operand again!
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}
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OS << TM.getInstrInfo().getName(getOpcode());
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OS << TM.getInstrInfo()->getName(getOpcode());
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for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
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const MachineOperand& mop = getOperand(i);
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@ -8,7 +8,7 @@
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##===----------------------------------------------------------------------===##
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LEVEL = ../..
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PARALLEL_DIRS = InstrSched SelectionDAG
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#PARALLEL_DIRS = InstrSched SelectionDAG
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LIBRARYNAME = codegen
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include $(LEVEL)/Makefile.common
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@ -66,7 +66,7 @@ bool PNE::EliminatePHINodes(MachineFunction &MF, MachineBasicBlock &MBB) {
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return false; // Quick exit for normal case...
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LiveVariables *LV = getAnalysisToUpdate<LiveVariables>();
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const TargetInstrInfo &MII = MF.getTarget().getInstrInfo();
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const TargetInstrInfo &MII = *MF.getTarget().getInstrInfo();
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const MRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
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// VRegPHIUseCount - Keep track of the number of times each virtual register
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@ -82,7 +82,7 @@ FunctionPass *llvm::createPrologEpilogCodeInserter() { return new PEI(); }
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///
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void PEI::saveCallerSavedRegisters(MachineFunction &Fn) {
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const MRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
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const TargetFrameInfo &FrameInfo = Fn.getTarget().getFrameInfo();
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const TargetFrameInfo &FrameInfo = *Fn.getTarget().getFrameInfo();
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// Get the callee saved register list...
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const unsigned *CSRegs = RegInfo->getCalleeSaveRegs();
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@ -170,7 +170,7 @@ void PEI::saveCallerSavedRegisters(MachineFunction &Fn) {
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}
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// Add code to restore the callee-save registers in each exiting block.
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const TargetInstrInfo &TII = Fn.getTarget().getInstrInfo();
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const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo();
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for (MachineFunction::iterator FI = Fn.begin(), E = Fn.end(); FI != E; ++FI) {
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// If last instruction is a return instruction, add an epilogue
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if (!FI->empty() && TII.isReturn(FI->back().getOpcode())) {
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@ -191,7 +191,7 @@ void PEI::saveCallerSavedRegisters(MachineFunction &Fn) {
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/// abstract stack objects...
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///
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void PEI::calculateFrameObjectOffsets(MachineFunction &Fn) {
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const TargetFrameInfo &TFI = Fn.getTarget().getFrameInfo();
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const TargetFrameInfo &TFI = *Fn.getTarget().getFrameInfo();
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bool StackGrowsDown =
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TFI.getStackGrowthDirection() == TargetFrameInfo::StackGrowsDown;
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@ -245,7 +245,7 @@ void PEI::insertPrologEpilogCode(MachineFunction &Fn) {
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Fn.getTarget().getRegisterInfo()->emitPrologue(Fn);
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// Add epilogue to restore the callee-save registers in each exiting block
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const TargetInstrInfo &TII = Fn.getTarget().getInstrInfo();
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const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo();
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for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
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// If last instruction is a return instruction, add an epilogue
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if (!I->empty() && TII.isReturn(I->back().getOpcode()))
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@ -520,7 +520,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
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// loop over each instruction
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MachineBasicBlock::iterator MI = MBB.begin();
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for (; MI != MBB.end(); ++MI) {
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const TargetInstrDescriptor &TID = TM->getInstrInfo().get(MI->getOpcode());
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const TargetInstrDescriptor &TID = TM->getInstrInfo()->get(MI->getOpcode());
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DEBUG(std::cerr << "\nStarting RegAlloc of: " << *MI;
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std::cerr << " Regs have values: ";
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for (unsigned i = 0; i != RegInfo->getNumRegs(); ++i)
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@ -159,7 +159,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
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// a preliminary pass that will invalidate any registers that
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// are used by the instruction (including implicit uses)
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unsigned Opcode = MI->getOpcode();
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const TargetInstrDescriptor &Desc = TM->getInstrInfo().get(Opcode);
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const TargetInstrDescriptor &Desc = TM->getInstrInfo()->get(Opcode);
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const unsigned *Regs = Desc.ImplicitUses;
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while (*Regs)
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RegsUsed[*Regs++] = true;
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@ -184,7 +184,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
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unsigned physReg = Virt2PhysRegMap[virtualReg];
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if (physReg == 0) {
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if (op.isDef()) {
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if (!TM->getInstrInfo().isTwoAddrInstr(MI->getOpcode()) || i) {
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if (!TM->getInstrInfo()->isTwoAddrInstr(MI->getOpcode()) || i) {
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physReg = getFreeReg(virtualReg);
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} else {
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// must be same register number as the first operand
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@ -77,7 +77,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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DEBUG(std::cerr << "Machine Function\n");
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const TargetMachine &TM = MF.getTarget();
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const MRegisterInfo &MRI = *TM.getRegisterInfo();
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const TargetInstrInfo &TII = TM.getInstrInfo();
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const TargetInstrInfo &TII = *TM.getInstrInfo();
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LiveVariables* LV = getAnalysisToUpdate<LiveVariables>();
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bool MadeChange = false;
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@ -191,7 +191,7 @@ namespace {
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bool runOnMachineFunction(MachineFunction& mf, const VirtRegMap& vrm) {
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mf_ = &mf;
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tm_ = &mf_->getTarget();
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tii_ = &tm_->getInstrInfo();
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tii_ = tm_->getInstrInfo();
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mri_ = tm_->getRegisterInfo();
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vrm_ = &vrm;
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p2vMap_.assign(mri_->getNumRegs(), 0);
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