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R600/SI: Make fitsRegClass() operands const
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182282 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -513,7 +513,7 @@ bool SITargetLowering::foldImm(SDValue &Operand, int32_t &Immediate,
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/// \brief Does "Op" fit into register class "RegClass" ?
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bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, SDValue &Op,
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bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
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unsigned RegClass) const {
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MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
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@ -30,7 +30,8 @@ class SITargetLowering : public AMDGPUTargetLowering {
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bool foldImm(SDValue &Operand, int32_t &Immediate,
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bool &ScalarSlotUsed) const;
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bool fitsRegClass(SelectionDAG &DAG, SDValue &Op, unsigned RegClass) const;
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bool fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
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unsigned RegClass) const;
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void ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
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unsigned RegClass, bool &ScalarSlotUsed) const;
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