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R600/SI: Make fitsRegClass() operands const

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Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182282 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2013-05-20 15:02:01 +00:00
parent 30a7a7c1fd
commit 9bf4590aaa
2 changed files with 3 additions and 2 deletions
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2
lib/Target/R600/SIISelLowering.cpp
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@ -513,7 +513,7 @@ bool SITargetLowering::foldImm(SDValue &Operand, int32_t &Immediate,
}
/// \brief Does "Op" fit into register class "RegClass" ?
bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, SDValue &Op,
bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
unsigned RegClass) const {
MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();

3
lib/Target/R600/SIISelLowering.h
View File

@ -30,7 +30,8 @@ class SITargetLowering : public AMDGPUTargetLowering {
bool foldImm(SDValue &Operand, int32_t &Immediate,
bool &ScalarSlotUsed) const;
bool fitsRegClass(SelectionDAG &DAG, SDValue &Op, unsigned RegClass) const;
bool fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
unsigned RegClass) const;
void ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
unsigned RegClass, bool &ScalarSlotUsed) const;