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[mips] Refactor SLT (set on less than) instructions. Separate encoding

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170664 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2012-12-20 04:27:52 +00:00
parent c23061547d
commit 9bf571fe2c
3 changed files with 32 additions and 22 deletions
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10
lib/Target/Mips/Mips64InstrInfo.td
View File

@ -86,8 +86,10 @@ def DADDiu : ArithLogicI<"daddiu", simm16_64, CPU64Regs, immSExt16, add>,
ADDI_FM<0x19>, IsAsCheapAsAMove;
def DANDi : ArithLogicI<"andi", uimm16_64, CPU64Regs, immZExt16, and>,
ADDI_FM<0xc>;
def SLTi64 : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>;
def SLTiu64 : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>;
def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, CPU64Regs>,
SLTI_FM<0xa>;
def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, CPU64Regs>,
SLTI_FM<0xb>;
def ORi64 : ArithLogicI<"ori", uimm16_64, CPU64Regs, immZExt16, or>,
ADDI_FM<0xd>;
def XORi64 : ArithLogicI<"xori", uimm16_64, CPU64Regs, immZExt16, xor>,
@ -98,8 +100,8 @@ def LUi64 : LoadUpper<0x0f, "lui", CPU64Regs, uimm16_64>;
def DADD : ArithLogicR<"dadd", CPU64Regs>, ADD_FM<0, 0x2c>;
def DADDu : ArithLogicR<"daddu", CPU64Regs, 1, IIAlu, add>, ADD_FM<0, 0x2d>;
def DSUBu : ArithLogicR<"dsubu", CPU64Regs, 0, IIAlu, sub>, ADD_FM<0, 0x2f>;
def SLT64 : SetCC_R<0x00, 0x2a, "slt", setlt, CPU64Regs>;
def SLTu64 : SetCC_R<0x00, 0x2b, "sltu", setult, CPU64Regs>;
def SLT64 : SetCC_R<"slt", setlt, CPU64Regs>, ADD_FM<0, 0x2a>;
def SLTu64 : SetCC_R<"sltu", setult, CPU64Regs>, ADD_FM<0, 0x2b>;
def AND64 : ArithLogicR<"and", CPU64Regs, 1, IIAlu, and>, ADD_FM<0, 0x24>;
def OR64 : ArithLogicR<"or", CPU64Regs, 1, IIAlu, or>, ADD_FM<0, 0x25>;
def XOR64 : ArithLogicR<"xor", CPU64Regs, 1, IIAlu, xor>, ADD_FM<0, 0x26>;

13
lib/Target/Mips/MipsInstrFormats.td
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@ -290,6 +290,19 @@ class B_FM {
let Inst{15-0} = offset;
}
class SLTI_FM<bits<6> op> {
bits<5> rt;
bits<5> rs;
bits<16> imm16;
bits<32> Inst;
let Inst{31-26} = op;
let Inst{25-21} = rs;
let Inst{20-16} = rt;
let Inst{15-0} = imm16;
}
//===----------------------------------------------------------------------===//
//
// FLOATING POINT INSTRUCTION FORMATS

31
lib/Target/Mips/MipsInstrInfo.td
View File

@ -567,21 +567,16 @@ class CBranchZero<string opstr, PatFrag cond_op, RegisterClass RC> :
}
// SetCC
class SetCC_R<bits<6> op, bits<6> func, string instr_asm, PatFrag cond_op,
RegisterClass RC>:
FR<op, func, (outs CPURegs:$rd), (ins RC:$rs, RC:$rt),
!strconcat(instr_asm, "\t$rd, $rs, $rt"),
[(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))],
IIAlu> {
let shamt = 0;
}
class SetCC_R<string opstr, PatFrag cond_op, RegisterClass RC> :
InstSE<(outs CPURegs:$rd), (ins RC:$rs, RC:$rt),
!strconcat(opstr, "\t$rd, $rs, $rt"),
[(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))], IIAlu, FrmR>;
class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od,
PatLeaf imm_type, RegisterClass RC>:
FI<op, (outs CPURegs:$rt), (ins RC:$rs, Od:$imm16),
!strconcat(instr_asm, "\t$rt, $rs, $imm16"),
[(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))],
IIAlu>;
class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
RegisterClass RC>:
InstSE<(outs CPURegs:$rt), (ins RC:$rs, Od:$imm16),
!strconcat(opstr, "\t$rt, $rs, $imm16"),
[(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))], IIAlu, FrmI>;
// Jump
class JumpFJ<bits<6> op, DAGOperand opnd, string instr_asm,
@ -897,8 +892,8 @@ def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegs>;
def ADDiu : ArithLogicI<"addiu", simm16, CPURegs, immSExt16, add>,
ADDI_FM<0x9>, IsAsCheapAsAMove;
def ADDi : ArithLogicI<"addi", simm16, CPURegs>, ADDI_FM<0x8>;
def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>;
def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>;
def SLTi : SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>, SLTI_FM<0xa>;
def SLTiu : SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>, SLTI_FM<0xb>;
def ANDi : ArithLogicI<"andi", uimm16, CPURegs, immZExt16, and>, ADDI_FM<0xc>;
def ORi : ArithLogicI<"ori", uimm16, CPURegs, immZExt16, or>, ADDI_FM<0xd>;
def XORi : ArithLogicI<"xori", uimm16, CPURegs, immZExt16, xor>, ADDI_FM<0xe>;
@ -909,8 +904,8 @@ def ADDu : ArithLogicR<"addu", CPURegs, 1, IIAlu, add>, ADD_FM<0, 0x21>;
def SUBu : ArithLogicR<"subu", CPURegs, 0, IIAlu, sub>, ADD_FM<0, 0x23>;
def ADD : ArithLogicR<"add", CPURegs>, ADD_FM<0, 0x20>;
def SUB : ArithLogicR<"sub", CPURegs>, ADD_FM<0, 0x22>;
def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>;
def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>;
def SLT : SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>;
def SLTu : SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>;
def AND : ArithLogicR<"and", CPURegs, 1, IIAlu, and>, ADD_FM<0, 0x24>;
def OR : ArithLogicR<"or", CPURegs, 1, IIAlu, or>, ADD_FM<0, 0x25>;
def XOR : ArithLogicR<"xor", CPURegs, 1, IIAlu, xor>, ADD_FM<0, 0x26>;