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TargetLowering::ComputeMaskedBits was not clearing reciprocal bits on shifts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28765 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -780,12 +780,14 @@ void TargetLowering::ComputeMaskedBits(SDOperand Op, uint64_t Mask,
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case ISD::SHL:
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// (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0
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if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
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uint64_t LowBits = (1ULL << SA->getValue())-1;
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Mask >>= SA->getValue();
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ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
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assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
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KnownZero <<= SA->getValue();
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KnownOne <<= SA->getValue();
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KnownZero |= (1ULL << SA->getValue())-1; // low bits known zero.
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KnownZero |= LowBits; // low bits known zero
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KnownOne &= ~LowBits; // and known not to be one.
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}
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return;
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case ISD::SRL:
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@ -798,7 +800,8 @@ void TargetLowering::ComputeMaskedBits(SDOperand Op, uint64_t Mask,
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assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
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KnownZero >>= SA->getValue();
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KnownOne >>= SA->getValue();
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KnownZero |= HighBits; // high bits known zero.
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KnownZero |= HighBits; // high bits known zero
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KnownOne &= ~HighBits; // and known not to be one.
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}
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return;
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case ISD::SRA:
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@ -815,10 +818,12 @@ void TargetLowering::ComputeMaskedBits(SDOperand Op, uint64_t Mask,
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uint64_t SignBit = 1ULL << (MVT::getSizeInBits(Op.getValueType())-1);
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SignBit >>= SA->getValue(); // Adjust to where it is now in the mask.
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if (KnownZero & SignBit) { // New bits are known zero.
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KnownZero |= HighBits;
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} else if (KnownOne & SignBit) { // New bits are known one.
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KnownOne |= HighBits;
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if (KnownZero & SignBit) {
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KnownZero |= HighBits; // New bits are known zero
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KnownOne &= ~HighBits; // and known not to be one.
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} else if (KnownOne & SignBit) {
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KnownOne |= HighBits; // New bits are known one
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KnownZero &= ~HighBits; // and known not to be zero.
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}
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}
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return;
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