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https://github.com/c64scene-ar/llvm-6502.git
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Teach the MBlaze asm parser how to parse special purpose register names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122261 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Wesley Peck
parent
025cc6e1be
commit
9c0068f0a3
@ -83,7 +83,6 @@ def brtarget : Operand<OtherVT>;
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def calltarget : Operand<i32>;
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def simm16 : Operand<i32>;
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def uimm5 : Operand<i32>;
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def uimm14 : Operand<i32>;
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def uimm15 : Operand<i32>;
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def fimm : Operand<f32>;
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@ -600,11 +599,11 @@ let isCodeGenOnly=1 in {
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//===----------------------------------------------------------------------===//
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// Misc. instructions
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//===----------------------------------------------------------------------===//
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def MFS : SPC<0x25, 0x2, (outs GPR:$dst), (ins uimm14:$rg),
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"mfs $dst, $rg", [], IIAlu>;
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def MFS : SPC<0x25, 0x2, (outs GPR:$dst), (ins SPR:$src),
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"mfs $dst, $src", [], IIAlu>;
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def MTS : SPC<0x25, 0x3, (outs), (ins uimm14:$dst, GPR:$rg),
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"mts $dst, $rg", [], IIAlu>;
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def MTS : SPC<0x25, 0x3, (outs SPR:$dst), (ins GPR:$src),
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"mts $dst, $src", [], IIAlu>;
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def MSRSET : MSR<0x25, 0x20, (outs GPR:$dst), (ins uimm15:$set),
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"msrset $dst, $set", [], IIAlu>;
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@ -48,38 +48,62 @@ MBlazeRegisterInfo(const MBlazeSubtarget &ST, const TargetInstrInfo &tii)
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/// MBlaze::R0, return the number that it corresponds to (e.g. 0).
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unsigned MBlazeRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
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switch (RegEnum) {
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case MBlaze::R0 : return 0;
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case MBlaze::R1 : return 1;
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case MBlaze::R2 : return 2;
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case MBlaze::R3 : return 3;
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case MBlaze::R4 : return 4;
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case MBlaze::R5 : return 5;
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case MBlaze::R6 : return 6;
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case MBlaze::R7 : return 7;
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case MBlaze::R8 : return 8;
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case MBlaze::R9 : return 9;
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case MBlaze::R10 : return 10;
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case MBlaze::R11 : return 11;
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case MBlaze::R12 : return 12;
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case MBlaze::R13 : return 13;
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case MBlaze::R14 : return 14;
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case MBlaze::R15 : return 15;
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case MBlaze::R16 : return 16;
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case MBlaze::R17 : return 17;
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case MBlaze::R18 : return 18;
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case MBlaze::R19 : return 19;
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case MBlaze::R20 : return 20;
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case MBlaze::R21 : return 21;
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case MBlaze::R22 : return 22;
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case MBlaze::R23 : return 23;
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case MBlaze::R24 : return 24;
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case MBlaze::R25 : return 25;
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case MBlaze::R26 : return 26;
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case MBlaze::R27 : return 27;
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case MBlaze::R28 : return 28;
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case MBlaze::R29 : return 29;
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case MBlaze::R30 : return 30;
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case MBlaze::R31 : return 31;
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case MBlaze::R0 : return 0;
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case MBlaze::R1 : return 1;
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case MBlaze::R2 : return 2;
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case MBlaze::R3 : return 3;
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case MBlaze::R4 : return 4;
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case MBlaze::R5 : return 5;
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case MBlaze::R6 : return 6;
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case MBlaze::R7 : return 7;
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case MBlaze::R8 : return 8;
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case MBlaze::R9 : return 9;
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case MBlaze::R10 : return 10;
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case MBlaze::R11 : return 11;
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case MBlaze::R12 : return 12;
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case MBlaze::R13 : return 13;
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case MBlaze::R14 : return 14;
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case MBlaze::R15 : return 15;
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case MBlaze::R16 : return 16;
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case MBlaze::R17 : return 17;
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case MBlaze::R18 : return 18;
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case MBlaze::R19 : return 19;
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case MBlaze::R20 : return 20;
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case MBlaze::R21 : return 21;
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case MBlaze::R22 : return 22;
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case MBlaze::R23 : return 23;
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case MBlaze::R24 : return 24;
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case MBlaze::R25 : return 25;
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case MBlaze::R26 : return 26;
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case MBlaze::R27 : return 27;
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case MBlaze::R28 : return 28;
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case MBlaze::R29 : return 29;
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case MBlaze::R30 : return 30;
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case MBlaze::R31 : return 31;
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case MBlaze::RPC : return 0x0000;
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case MBlaze::RMSR : return 0x0001;
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case MBlaze::REAR : return 0x0003;
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case MBlaze::RESR : return 0x0005;
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case MBlaze::RFSR : return 0x0007;
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case MBlaze::RBTR : return 0x000B;
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case MBlaze::REDR : return 0x000D;
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case MBlaze::RPID : return 0x1000;
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case MBlaze::RZPR : return 0x1001;
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case MBlaze::RTLBX : return 0x1002;
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case MBlaze::RTLBLO : return 0x1003;
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case MBlaze::RTLBHI : return 0x1004;
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case MBlaze::RPVR0 : return 0x2000;
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case MBlaze::RPVR1 : return 0x2001;
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case MBlaze::RPVR2 : return 0x2002;
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case MBlaze::RPVR3 : return 0x2003;
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case MBlaze::RPVR4 : return 0x2004;
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case MBlaze::RPVR5 : return 0x2005;
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case MBlaze::RPVR6 : return 0x2006;
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case MBlaze::RPVR7 : return 0x2007;
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case MBlaze::RPVR8 : return 0x2008;
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case MBlaze::RPVR9 : return 0x2009;
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case MBlaze::RPVR10 : return 0x200A;
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case MBlaze::RPVR11 : return 0x200B;
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default: llvm_unreachable("Unknown register number!");
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}
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return 0; // Not reached
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@ -126,6 +150,37 @@ unsigned MBlazeRegisterInfo::getRegisterFromNumbering(unsigned Reg) {
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return 0; // Not reached
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}
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unsigned MBlazeRegisterInfo::getSpecialRegisterFromNumbering(unsigned Reg) {
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switch (Reg) {
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case 0x0000 : return MBlaze::RPC;
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case 0x0001 : return MBlaze::RMSR;
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case 0x0003 : return MBlaze::REAR;
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case 0x0005 : return MBlaze::RESR;
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case 0x0007 : return MBlaze::RFSR;
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case 0x000B : return MBlaze::RBTR;
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case 0x000D : return MBlaze::REDR;
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case 0x1000 : return MBlaze::RPID;
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case 0x1001 : return MBlaze::RZPR;
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case 0x1002 : return MBlaze::RTLBX;
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case 0x1003 : return MBlaze::RTLBLO;
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case 0x1004 : return MBlaze::RTLBHI;
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case 0x2000 : return MBlaze::RPVR0;
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case 0x2001 : return MBlaze::RPVR1;
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case 0x2002 : return MBlaze::RPVR2;
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case 0x2003 : return MBlaze::RPVR3;
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case 0x2004 : return MBlaze::RPVR4;
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case 0x2005 : return MBlaze::RPVR5;
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case 0x2006 : return MBlaze::RPVR6;
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case 0x2007 : return MBlaze::RPVR7;
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case 0x2008 : return MBlaze::RPVR8;
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case 0x2009 : return MBlaze::RPVR9;
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case 0x200A : return MBlaze::RPVR10;
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case 0x200B : return MBlaze::RPVR11;
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default: llvm_unreachable("Unknown register number!");
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}
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return 0; // Not reached
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}
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unsigned MBlazeRegisterInfo::getPICCallReg() {
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return MBlaze::R20;
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}
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@ -44,6 +44,7 @@ struct MBlazeRegisterInfo : public MBlazeGenRegisterInfo {
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/// MBlaze::RA, return the number that it corresponds to (e.g. 31).
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static unsigned getRegisterNumbering(unsigned RegEnum);
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static unsigned getRegisterFromNumbering(unsigned RegEnum);
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static unsigned getSpecialRegisterFromNumbering(unsigned RegEnum);
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/// Get PIC indirect call register
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static unsigned getPICCallReg();
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@ -82,7 +82,7 @@ let Namespace = "MBlaze" in {
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def REDR : MBlazeSPRReg<0x000D, "redr">, DwarfRegNum<[38]>;
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def RPID : MBlazeSPRReg<0x1000, "rpid">, DwarfRegNum<[39]>;
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def RZPR : MBlazeSPRReg<0x1001, "rzpr">, DwarfRegNum<[40]>;
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def RTLBX : MBlazeSPRReg<0x0002, "rtlbx">, DwarfRegNum<[41]>;
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def RTLBX : MBlazeSPRReg<0x1002, "rtlbx">, DwarfRegNum<[41]>;
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def RTLBLO : MBlazeSPRReg<0x1003, "rtlblo">, DwarfRegNum<[42]>;
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def RTLBHI : MBlazeSPRReg<0x1004, "rtlbhi">, DwarfRegNum<[43]>;
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def RPVR0 : MBlazeSPRReg<0x2000, "rpvr0">, DwarfRegNum<[44]>;
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@ -138,3 +138,44 @@ def GPR : RegisterClass<"MBlaze", [i32,f32], 32,
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}
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}];
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}
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def SPR : RegisterClass<"MBlaze", [i32], 32,
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[
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// Reserved
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RPC,
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RMSR,
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REAR,
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RESR,
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RFSR,
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RBTR,
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REDR,
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RPID,
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RZPR,
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RTLBX,
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RTLBLO,
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RTLBHI,
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RPVR0,
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RPVR1,
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RPVR2,
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RPVR3,
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RPVR4,
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RPVR5,
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RPVR6,
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RPVR7,
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RPVR8,
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RPVR9,
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RPVR10,
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RPVR11
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]>
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{
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let MethodProtos = [{
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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SPRClass::iterator
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SPRClass::allocation_order_end(const MachineFunction &MF) const {
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// None of the special purpose registers are allocatable.
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return end()-24;
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}
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}];
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}
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@ -1,7 +1,7 @@
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# RUN: llvm-mc -triple mblaze-unknown-unknown -show-encoding %s | FileCheck %s
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# Test to ensure that all FPU instructions can be parsed by the
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# assembly parser correctly.
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# Test to ensure that all special instructions and special registers can be
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# parsed by the assembly parser correctly.
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# TYPE A: OPCODE RD RA RB FLAGS
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# BINARY: 011011 00000 00000 00000 00000000000
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@ -9,7 +9,7 @@
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# CHECK: mfs
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# BINARY: 100101 00000 00000 10000 00000000000
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# CHECK: encoding: [0x94,0x00,0x80,0x00]
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mfs r0, 0x0
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mfs r0, rpc
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# CHECK: msrclr
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# BINARY: 100101 00000 100010 000000000000000
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@ -24,7 +24,7 @@
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# CHECK: mts
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# BINARY: 100101 00000 00000 11 00000000000000
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# CHECK: encoding: [0x94,0x00,0xc0,0x00]
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mts 0x0 , r0
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mts rpc, r0
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# CHECK: wdc
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# BINARY: 100100 00000 00000 00001 00001100100
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@ -45,3 +45,123 @@
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# BINARY: 100100 00000 00000 00001 00001101000
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# CHECK: encoding: [0x90,0x00,0x08,0x68]
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wic r0, r1
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# CHECK: mfs
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# BINARY: 100101 00001 00000 10000 00000000000
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# CHECK: encoding: [0x94,0x20,0x80,0x00]
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mfs r1, rpc
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# CHECK: mfs
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# BINARY: 100101 00001 00000 10000 00000000001
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# CHECK: encoding: [0x94,0x20,0x80,0x01]
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mfs r1, rmsr
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# CHECK: mfs
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# BINARY: 100101 00001 00000 10000 00000000011
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# CHECK: encoding: [0x94,0x20,0x80,0x03]
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mfs r1, rear
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# CHECK: mfs
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# BINARY: 100101 00001 00000 10000 00000000101
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# CHECK: encoding: [0x94,0x20,0x80,0x05]
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mfs r1, resr
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# CHECK: mfs
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# BINARY: 100101 00001 00000 10000 00000000111
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# CHECK: encoding: [0x94,0x20,0x80,0x07]
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mfs r1, rfsr
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# CHECK: mfs
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# BINARY: 100101 00001 00000 10000 00000001011
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# CHECK: encoding: [0x94,0x20,0x80,0x0b]
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mfs r1, rbtr
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# CHECK: mfs
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# BINARY: 100101 00001 00000 10000 00000001101
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# CHECK: encoding: [0x94,0x20,0x80,0x0d]
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mfs r1, redr
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# CHECK: mfs
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# BINARY: 100101 00001 00000 10010 00000000000
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# CHECK: encoding: [0x94,0x20,0x90,0x00]
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mfs r1, rpid
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# CHECK: mfs
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# BINARY: 100101 00001 00000 10010 00000000001
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# CHECK: encoding: [0x94,0x20,0x90,0x01]
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mfs r1, rzpr
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# CHECK: mfs
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# BINARY: 100101 00001 00000 10010 00000000010
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# CHECK: encoding: [0x94,0x20,0x90,0x02]
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mfs r1, rtlbx
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# CHECK: mfs
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# BINARY: 100101 00001 00000 10010 00000000100
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# CHECK: encoding: [0x94,0x20,0x90,0x04]
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mfs r1, rtlbhi
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# CHECK: mfs
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# BINARY: 100101 00001 00000 10010 00000000011
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# CHECK: encoding: [0x94,0x20,0x90,0x03]
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mfs r1, rtlblo
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# CHECK: mfs
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# BINARY: 100101 00001 00000 10100 00000000000
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# CHECK: encoding: [0x94,0x20,0xa0,0x00]
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mfs r1, rpvr0
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# CHECK: mfs
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# BINARY: 100101 00001 00000 10100 00000000001
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# CHECK: encoding: [0x94,0x20,0xa0,0x01]
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mfs r1, rpvr1
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# CHECK: mfs
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# BINARY: 100101 00001 00000 10100 00000000010
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# CHECK: encoding: [0x94,0x20,0xa0,0x02]
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mfs r1, rpvr2
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# CHECK: mfs
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# BINARY: 100101 00001 00000 10100 00000000011
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# CHECK: encoding: [0x94,0x20,0xa0,0x03]
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mfs r1, rpvr3
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# CHECK: mfs
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# BINARY: 100101 00001 00000 10100 00000000100
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# CHECK: encoding: [0x94,0x20,0xa0,0x04]
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mfs r1, rpvr4
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# CHECK: mfs
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# BINARY: 100101 00001 00000 10100 00000000101
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# CHECK: encoding: [0x94,0x20,0xa0,0x05]
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mfs r1, rpvr5
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# CHECK: mfs
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# BINARY: 100101 00001 00000 10100 00000000110
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# CHECK: encoding: [0x94,0x20,0xa0,0x06]
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mfs r1, rpvr6
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# CHECK: mfs
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# BINARY: 100101 00001 00000 10100 00000000111
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# CHECK: encoding: [0x94,0x20,0xa0,0x07]
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mfs r1, rpvr7
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# CHECK: mfs
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# BINARY: 100101 00001 00000 10100 00000001000
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# CHECK: encoding: [0x94,0x20,0xa0,0x08]
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mfs r1, rpvr8
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# CHECK: mfs
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# BINARY: 100101 00001 00000 10100 00000001001
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# CHECK: encoding: [0x94,0x20,0xa0,0x09]
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mfs r1, rpvr9
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# CHECK: mfs
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# BINARY: 100101 00001 00000 10100 00000001010
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# CHECK: encoding: [0x94,0x20,0xa0,0x0a]
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mfs r1, rpvr10
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# CHECK: mfs
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# BINARY: 100101 00001 00000 10100 00000001011
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# CHECK: encoding: [0x94,0x20,0xa0,0x0b]
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mfs r1, rpvr11
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