From 9c044674e6349caff46fea79a103dfe210dfde56 Mon Sep 17 00:00:00 2001
From: Evan Cheng <evan.cheng@apple.com>
Date: Sat, 29 May 2010 01:35:22 +0000
Subject: [PATCH] Fix PR7193: if sibling call address can take a register, make
 sure there are enough registers available by counting inreg arguments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105092 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/X86/X86ISelLowering.cpp | 18 ++++++++++++++++++
 test/CodeGen/X86/sibcall-3.ll      | 16 ++++++++++++++++
 2 files changed, 34 insertions(+)
 create mode 100644 test/CodeGen/X86/sibcall-3.ll

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index a5fd1d1e7b5..0fd87bd7447 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -2427,6 +2427,24 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
         }
       }
     }
+
+    // If the tailcall address may be in a register, then make sure it's
+    // possible to register allocate for it. In 32-bit, the call address can
+    // only target EAX, EDX, or ECX since the tail call must be scheduled after
+    // callee-saved registers are restored. In 64-bit, it's RAX, RCX, RDX, RSI,
+    // RDI, R8, R9, R11.
+    if (!isa<GlobalAddressSDNode>(Callee) &&
+        !isa<ExternalSymbolSDNode>(Callee)) {
+      unsigned Limit = Subtarget->is64Bit() ? 8 : 3;
+      unsigned NumInRegs = 0;
+      for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
+        CCValAssign &VA = ArgLocs[i];
+        if (VA.isRegLoc()) {
+          if (++NumInRegs == Limit)
+            return false;
+        }
+      }
+    }
   }
 
   return true;
diff --git a/test/CodeGen/X86/sibcall-3.ll b/test/CodeGen/X86/sibcall-3.ll
new file mode 100644
index 00000000000..f0d66cf7b69
--- /dev/null
+++ b/test/CodeGen/X86/sibcall-3.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -mtriple=i386-unknown-unknown | FileCheck %s
+; PR7193
+
+define void @t1(i8* inreg %dst, i8* inreg %src, i8* inreg %len) nounwind {
+; CHECK: t1:
+; CHECK: call 0
+  tail call void null(i8* inreg %dst, i8* inreg %src, i8* inreg %len) nounwind
+  ret void
+}
+
+define void @t2(i8* inreg %dst, i8* inreg %src, i8* inreg %len) nounwind {
+; CHECK: t2:
+; CHECK: jmpl
+  tail call void null(i8* inreg %dst, i8* inreg %src) nounwind
+  ret void
+}