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teach the ppc backend how to spill/reload vector regs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26806 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -80,7 +80,7 @@ bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
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}
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unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI,
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int &FrameIndex) const {
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int &FrameIndex) const {
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switch (MI->getOpcode()) {
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default: break;
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case PPC::LD:
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@ -50,6 +50,9 @@ PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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unsigned SrcReg, int FrameIdx,
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const TargetRegisterClass *RC) const {
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if (SrcReg == PPC::LR) {
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// FIXME: this spills LR immediately to memory in one step. To do this, we
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// use R11, which we know cannot be used in the prolog/epilog. This is a
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// hack.
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BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
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addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
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} else if (RC == PPC::CRRCRegisterClass) {
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@ -63,6 +66,15 @@ PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx);
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} else if (RC == PPC::F4RCRegisterClass) {
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addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx);
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} else if (RC == PPC::VRRCRegisterClass) {
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// We don't have indexed addressing for vector loads. Emit:
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// R11 = ADDI FI#
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// Dest = LVX R0, R11
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//
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// FIXME: We use R0 here, because it isn't available for RA.
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addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
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BuildMI(MBB, MI, PPC::STVX, 3)
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.addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0);
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} else {
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assert(0 && "Unknown regclass!");
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abort();
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@ -88,6 +100,14 @@ PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx);
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} else if (RC == PPC::F4RCRegisterClass) {
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addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx);
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} else if (RC == PPC::VRRCRegisterClass) {
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// We don't have indexed addressing for vector loads. Emit:
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// R11 = ADDI FI#
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// Dest = LVX R0, R11
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//
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// FIXME: We use R0 here, because it isn't available for RA.
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addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
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BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0);
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} else {
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assert(0 && "Unknown regclass!");
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abort();
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