From 9c210dabdaee29f38437ad6f61865a5fce694d33 Mon Sep 17 00:00:00 2001 From: Christian Konig Date: Wed, 10 Apr 2013 08:39:01 +0000 Subject: [PATCH] R600/SI: remove image sample writemask MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Christian König Reviewed-by: Michel Dänzer git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179164 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/SIInstructions.td | 25 ++++++++++----------- lib/Target/R600/SIIntrinsics.td | 2 +- test/CodeGen/R600/llvm.SI.sample.ll | 34 ++++++++++++++--------------- 3 files changed, 30 insertions(+), 31 deletions(-) diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td index 6bae3be7743..e2a08fcca97 100644 --- a/lib/Target/R600/SIInstructions.td +++ b/lib/Target/R600/SIInstructions.td @@ -1219,49 +1219,48 @@ def : Pat < /* int_SI_sample for simple 1D texture lookup */ def : Pat < - (int_SI_sample imm:$writemask, VReg_32:$addr, - SReg_256:$rsrc, SReg_128:$sampler, imm), - (IMAGE_SAMPLE imm:$writemask, 0, 0, 0, 0, 0, 0, 0, VReg_32:$addr, + (int_SI_sample VReg_32:$addr, SReg_256:$rsrc, SReg_128:$sampler, imm), + (IMAGE_SAMPLE 0xf, 0, 0, 0, 0, 0, 0, 0, VReg_32:$addr, SReg_256:$rsrc, SReg_128:$sampler) >; class SamplePattern : Pat < - (name imm:$writemask, (addr_type addr_class:$addr), + (name (addr_type addr_class:$addr), SReg_256:$rsrc, SReg_128:$sampler, imm), - (opcode imm:$writemask, 0, 0, 0, 0, 0, 0, 0, addr_class:$addr, + (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, addr_class:$addr, SReg_256:$rsrc, SReg_128:$sampler) >; class SampleRectPattern : Pat < - (name imm:$writemask, (addr_type addr_class:$addr), + (name (addr_type addr_class:$addr), SReg_256:$rsrc, SReg_128:$sampler, TEX_RECT), - (opcode imm:$writemask, 1, 0, 0, 0, 0, 0, 0, addr_class:$addr, + (opcode 0xf, 1, 0, 0, 0, 0, 0, 0, addr_class:$addr, SReg_256:$rsrc, SReg_128:$sampler) >; class SampleArrayPattern : Pat < - (name imm:$writemask, (addr_type addr_class:$addr), + (name (addr_type addr_class:$addr), SReg_256:$rsrc, SReg_128:$sampler, TEX_ARRAY), - (opcode imm:$writemask, 0, 0, 1, 0, 0, 0, 0, addr_class:$addr, + (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, addr_class:$addr, SReg_256:$rsrc, SReg_128:$sampler) >; class SampleShadowPattern : Pat < - (name imm:$writemask, (addr_type addr_class:$addr), + (name (addr_type addr_class:$addr), SReg_256:$rsrc, SReg_128:$sampler, TEX_SHADOW), - (opcode imm:$writemask, 0, 0, 0, 0, 0, 0, 0, addr_class:$addr, + (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, addr_class:$addr, SReg_256:$rsrc, SReg_128:$sampler) >; class SampleShadowArrayPattern : Pat < - (name imm:$writemask, (addr_type addr_class:$addr), + (name (addr_type addr_class:$addr), SReg_256:$rsrc, SReg_128:$sampler, TEX_SHADOW_ARRAY), - (opcode imm:$writemask, 0, 0, 1, 0, 0, 0, 0, addr_class:$addr, + (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, addr_class:$addr, SReg_256:$rsrc, SReg_128:$sampler) >; diff --git a/lib/Target/R600/SIIntrinsics.td b/lib/Target/R600/SIIntrinsics.td index 0af378edfe2..16d9d812af9 100644 --- a/lib/Target/R600/SIIntrinsics.td +++ b/lib/Target/R600/SIIntrinsics.td @@ -19,7 +19,7 @@ let TargetPrefix = "SI", isTarget = 1 in { def int_SI_load_const : Intrinsic <[llvm_float_ty], [llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>; def int_SI_vs_load_input : Intrinsic <[llvm_v4f32_ty], [llvm_v16i8_ty, llvm_i16_ty, llvm_i32_ty], [IntrNoMem]> ; - class Sample : Intrinsic <[llvm_v4f32_ty], [llvm_i32_ty, llvm_anyvector_ty, llvm_v32i8_ty, llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>; + class Sample : Intrinsic <[llvm_v4f32_ty], [llvm_anyvector_ty, llvm_v32i8_ty, llvm_v16i8_ty, llvm_i32_ty], [IntrNoMem]>; def int_SI_sample : Sample; def int_SI_sampleb : Sample; diff --git a/test/CodeGen/R600/llvm.SI.sample.ll b/test/CodeGen/R600/llvm.SI.sample.ll index 5bdb246a37f..7c7aa5e002b 100644 --- a/test/CodeGen/R600/llvm.SI.sample.ll +++ b/test/CodeGen/R600/llvm.SI.sample.ll @@ -34,37 +34,37 @@ define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) { %v14 = insertelement <4 x i32> undef, i32 %a4, i32 1 %v15 = insertelement <4 x i32> undef, i32 %a4, i32 2 %v16 = insertelement <4 x i32> undef, i32 %a4, i32 3 - %res1 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v1, + %res1 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v1, <8 x i32> undef, <4 x i32> undef, i32 1) - %res2 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v2, + %res2 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v2, <8 x i32> undef, <4 x i32> undef, i32 2) - %res3 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v3, + %res3 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v3, <8 x i32> undef, <4 x i32> undef, i32 3) - %res4 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v4, + %res4 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v4, <8 x i32> undef, <4 x i32> undef, i32 4) - %res5 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v5, + %res5 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v5, <8 x i32> undef, <4 x i32> undef, i32 5) - %res6 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v6, + %res6 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v6, <8 x i32> undef, <4 x i32> undef, i32 6) - %res7 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v7, + %res7 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v7, <8 x i32> undef, <4 x i32> undef, i32 7) - %res8 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v8, + %res8 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v8, <8 x i32> undef, <4 x i32> undef, i32 8) - %res9 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v9, + %res9 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v9, <8 x i32> undef, <4 x i32> undef, i32 9) - %res10 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v10, + %res10 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v10, <8 x i32> undef, <4 x i32> undef, i32 10) - %res11 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v11, + %res11 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v11, <8 x i32> undef, <4 x i32> undef, i32 11) - %res12 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v12, + %res12 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v12, <8 x i32> undef, <4 x i32> undef, i32 12) - %res13 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v13, + %res13 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v13, <8 x i32> undef, <4 x i32> undef, i32 13) - %res14 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v14, + %res14 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v14, <8 x i32> undef, <4 x i32> undef, i32 14) - %res15 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v15, + %res15 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v15, <8 x i32> undef, <4 x i32> undef, i32 15) - %res16 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v16, + %res16 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v16, <8 x i32> undef, <4 x i32> undef, i32 16) %e1 = extractelement <4 x float> %res1, i32 0 %e2 = extractelement <4 x float> %res2, i32 0 @@ -101,6 +101,6 @@ define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) { ret void } -declare <4 x float> @llvm.SI.sample.(i32, <4 x i32>, <8 x i32>, <4 x i32>, i32) readnone +declare <4 x float> @llvm.SI.sample.(<4 x i32>, <8 x i32>, <4 x i32>, i32) readnone declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)