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Patterns to match AVX 256-bit horizontal arithmetic intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110427 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3415,24 +3415,22 @@ multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
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}
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let isAsmParserOnly = 1, Predicates = [HasAVX] in {
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defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
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int_x86_sse3_hadd_ps, 0>, VEX_4V;
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defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
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int_x86_sse3_hadd_pd, 0>, VEX_4V;
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defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
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int_x86_sse3_hsub_ps, 0>, VEX_4V;
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defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
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int_x86_sse3_hsub_pd, 0>, VEX_4V;
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let Pattern = []<dag> in {
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defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
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defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
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int_x86_sse3_hadd_ps, 0>, VEX_4V;
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defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
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defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
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int_x86_sse3_hadd_pd, 0>, VEX_4V;
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defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
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defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
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int_x86_sse3_hsub_ps, 0>, VEX_4V;
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defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
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defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
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int_x86_sse3_hsub_pd, 0>, VEX_4V;
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}
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defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
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int_x86_avx_hadd_ps_256, 0>, VEX_4V;
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defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
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int_x86_avx_hadd_pd_256, 0>, VEX_4V;
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defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
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int_x86_avx_hsub_ps_256, 0>, VEX_4V;
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defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
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int_x86_avx_hsub_pd_256, 0>, VEX_4V;
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}
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let Constraints = "$src1 = $dst" in {
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