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https://github.com/c64scene-ar/llvm-6502.git
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Use multiclass for post-increment store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173816 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jyotsna Verma
parent
30c3bbe007
commit
9c3846c99c
@ -608,8 +608,8 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, DebugLoc dl) {
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// Offset value must be within representable range
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// and must have correct alignment properties.
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if (TII->isValidAutoIncImm(StoredVT, Val)) {
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SDValue Ops[] = { Value, Base,
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CurDAG->getTargetConstant(Val, MVT::i32), Chain};
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SDValue Ops[] = {Base, CurDAG->getTargetConstant(Val, MVT::i32), Value,
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Chain};
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unsigned Opcode = 0;
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// Figure out the post inc version of opcode.
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@ -46,11 +46,10 @@ class NVInstPost_V4<dag outs, dag ins, string asmstr, list<dag> pattern,
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}
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// Post increment ST Instruction.
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class NVInstPI_V4<dag outs, dag ins, string asmstr, list<dag> pattern,
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string cstr>
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: NVInstPost_V4<outs, ins, asmstr, pattern, cstr> {
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let rt{0-4} = 0;
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}
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let mayStore = 1 in
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class NVInstPI_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: NVInstPost_V4<outs, ins, asmstr, pattern, cstr>;
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class MEMInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstHexagon<outs, ins, asmstr, pattern, "", MEM_V4, TypeMEMOP> {
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@ -1419,35 +1419,71 @@ def STd_GP : STInst2<(outs),
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[]>,
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Requires<[NoV4T]>;
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let hasCtrlDep = 1, isPredicable = 1 in
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def POST_STdri : STInstPI<(outs IntRegs:$dst),
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(ins DoubleRegs:$src1, IntRegs:$src2, s4Imm:$offset),
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"memd($src2++#$offset) = $src1",
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[(set IntRegs:$dst,
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(post_store (i64 DoubleRegs:$src1), (i32 IntRegs:$src2),
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s4_3ImmPred:$offset))],
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//===----------------------------------------------------------------------===//
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// Post increment store
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//===----------------------------------------------------------------------===//
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multiclass ST_PostInc_Pbase<string mnemonic, RegisterClass RC, Operand ImmOp,
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bit isNot, bit isPredNew> {
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let PNewValue = !if(isPredNew, "new", "") in
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def NAME : STInst2PI<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
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!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
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") ")#mnemonic#"($src2++#$offset) = $src3",
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[],
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"$src2 = $dst">;
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}
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// if ([!]Pv) memd(Rx++#s4:3)=Rtt
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// if (Pv) memd(Rx++#s4:3)=Rtt
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let AddedComplexity = 10, neverHasSideEffects = 1,
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isPredicated = 1 in
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def POST_STdri_cPt : STInst2PI<(outs IntRegs:$dst),
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(ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
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s4_3Imm:$offset),
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"if ($src1) memd($src3++#$offset) = $src2",
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[],
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"$src3 = $dst">;
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multiclass ST_PostInc_Pred<string mnemonic, RegisterClass RC,
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Operand ImmOp, bit PredNot> {
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let PredSense = !if(PredNot, "false", "true") in {
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defm _c#NAME# : ST_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 0>;
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// Predicate new
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let Predicates = [HasV4T], validSubTargets = HasV4SubT in
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defm _cdn#NAME#_V4 : ST_PostInc_Pbase<mnemonic, RC, ImmOp, PredNot, 1>;
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}
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}
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// if (!Pv) memd(Rx++#s4:3)=Rtt
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let AddedComplexity = 10, neverHasSideEffects = 1, isPredicated = 1,
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isPredicated = 1 in
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def POST_STdri_cNotPt : STInst2PI<(outs IntRegs:$dst),
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(ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
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s4_3Imm:$offset),
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"if (!$src1) memd($src3++#$offset) = $src2",
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[],
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"$src3 = $dst">;
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let hasCtrlDep = 1, isNVStorable = 1, neverHasSideEffects = 1 in
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multiclass ST_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
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Operand ImmOp> {
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let hasCtrlDep = 1, BaseOpcode = "POST_"#BaseOp in {
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let isPredicable = 1 in
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def NAME : STInst2PI<(outs IntRegs:$dst),
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(ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
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#mnemonic#"($src1++#$offset) = $src2",
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[],
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"$src1 = $dst">;
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let isPredicated = 1 in {
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defm Pt : ST_PostInc_Pred<mnemonic, RC, ImmOp, 0 >;
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defm NotPt : ST_PostInc_Pred<mnemonic, RC, ImmOp, 1 >;
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}
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}
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}
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defm POST_STbri: ST_PostInc <"memb", "STrib", IntRegs, s4_0Imm>, AddrModeRel;
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defm POST_SThri: ST_PostInc <"memh", "STrih", IntRegs, s4_1Imm>, AddrModeRel;
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defm POST_STwri: ST_PostInc <"memw", "STriw", IntRegs, s4_2Imm>, AddrModeRel;
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let isNVStorable = 0 in
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defm POST_STdri: ST_PostInc <"memd", "STrid", DoubleRegs, s4_3Imm>, AddrModeRel;
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def : Pat<(post_truncsti8 (i32 IntRegs:$src1), IntRegs:$src2,
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s4_3ImmPred:$offset),
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(POST_STbri IntRegs:$src2, s4_0ImmPred:$offset, IntRegs:$src1)>;
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def : Pat<(post_truncsti16 (i32 IntRegs:$src1), IntRegs:$src2,
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s4_3ImmPred:$offset),
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(POST_SThri IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
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def : Pat<(post_store (i32 IntRegs:$src1), IntRegs:$src2, s4_2ImmPred:$offset),
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(POST_STwri IntRegs:$src2, s4_1ImmPred:$offset, IntRegs:$src1)>;
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def : Pat<(post_store (i64 DoubleRegs:$src1), IntRegs:$src2,
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s4_3ImmPred:$offset),
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(POST_STdri IntRegs:$src2, s4_3ImmPred:$offset, DoubleRegs:$src1)>;
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//===----------------------------------------------------------------------===//
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// multiclass for the store instructions with MEMri operand.
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@ -1609,32 +1645,6 @@ def STb_GP : STInst2<(outs),
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[]>,
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Requires<[NoV4T]>;
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// memb(Rx++#s4:0)=Rt
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let hasCtrlDep = 1, isPredicable = 1 in
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def POST_STbri : STInstPI<(outs IntRegs:$dst), (ins IntRegs:$src1,
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IntRegs:$src2,
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s4Imm:$offset),
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"memb($src2++#$offset) = $src1",
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[(set IntRegs:$dst,
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(post_truncsti8 (i32 IntRegs:$src1), (i32 IntRegs:$src2),
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s4_0ImmPred:$offset))],
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"$src2 = $dst">;
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// if ([!]Pv) memb(Rx++#s4:0)=Rt
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// if (Pv) memb(Rx++#s4:0)=Rt
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let hasCtrlDep = 1, isPredicated = 1 in
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def POST_STbri_cPt : STInst2PI<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
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"if ($src1) memb($src3++#$offset) = $src2",
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[],"$src3 = $dst">;
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// if (!Pv) memb(Rx++#s4:0)=Rt
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let hasCtrlDep = 1, isPredicated = 1 in
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def POST_STbri_cNotPt : STInst2PI<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
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"if (!$src1) memb($src3++#$offset) = $src2",
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[],"$src3 = $dst">;
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let neverHasSideEffects = 1 in
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def STrih_GP : STInst2<(outs),
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(ins globaladdress:$global, u16Imm:$offset, IntRegs:$src),
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@ -1650,31 +1660,6 @@ def STh_GP : STInst2<(outs),
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Requires<[NoV4T]>;
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// memh(Rx++#s4:1)=Rt.H
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// memh(Rx++#s4:1)=Rt
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let hasCtrlDep = 1, isPredicable = 1 in
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def POST_SThri : STInstPI<(outs IntRegs:$dst),
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(ins IntRegs:$src1, IntRegs:$src2, s4Imm:$offset),
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"memh($src2++#$offset) = $src1",
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[(set IntRegs:$dst,
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(post_truncsti16 (i32 IntRegs:$src1), (i32 IntRegs:$src2),
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s4_1ImmPred:$offset))],
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"$src2 = $dst">;
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// if ([!]Pv) memh(Rx++#s4:1)=Rt
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// if (Pv) memh(Rx++#s4:1)=Rt
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let hasCtrlDep = 1, isPredicated = 1 in
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def POST_SThri_cPt : STInst2PI<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
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"if ($src1) memh($src3++#$offset) = $src2",
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[],"$src3 = $dst">;
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// if (!Pv) memh(Rx++#s4:1)=Rt
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let hasCtrlDep = 1, isPredicated = 1 in
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def POST_SThri_cNotPt : STInst2PI<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
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"if (!$src1) memh($src3++#$offset) = $src2",
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[],"$src3 = $dst">;
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// Store word.
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// Store predicate.
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@ -1698,32 +1683,6 @@ def STw_GP : STInst2<(outs),
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[]>,
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Requires<[NoV4T]>;
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let hasCtrlDep = 1, isPredicable = 1 in
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def POST_STwri : STInstPI<(outs IntRegs:$dst),
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(ins IntRegs:$src1, IntRegs:$src2, s4Imm:$offset),
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"memw($src2++#$offset) = $src1",
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[(set IntRegs:$dst,
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(post_store (i32 IntRegs:$src1), (i32 IntRegs:$src2),
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s4_2ImmPred:$offset))],
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"$src2 = $dst">;
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// if ([!]Pv) memw(Rx++#s4:2)=Rt
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// if (Pv) memw(Rx++#s4:2)=Rt
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let hasCtrlDep = 1, isPredicated = 1 in
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def POST_STwri_cPt : STInst2PI<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
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"if ($src1) memw($src3++#$offset) = $src2",
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[],"$src3 = $dst">;
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// if (!Pv) memw(Rx++#s4:2)=Rt
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let hasCtrlDep = 1, isPredicated = 1 in
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def POST_STwri_cNotPt : STInst2PI<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
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"if (!$src1) memw($src3++#$offset) = $src2",
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[],"$src3 = $dst">;
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// Allocate stack frame.
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let Defs = [R29, R30], Uses = [R31, R30], neverHasSideEffects = 1 in {
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def ALLOCFRAME : STInst2<(outs),
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@ -1652,34 +1652,12 @@ def STrid_shl_V4 : STInst<(outs),
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// if ([!]Pv[.new]) memd(#u6)=Rtt
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// TODO: needs to be implemented.
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// if ([!]Pv[.new]) memd(Rx++#s4:3)=Rtt
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// if (Pv) memd(Rx++#s4:3)=Rtt
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// if (Pv.new) memd(Rx++#s4:3)=Rtt
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let AddedComplexity = 10, neverHasSideEffects = 1,
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isPredicated = 1 in
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def POST_STdri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
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(ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
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s4_3Imm:$offset),
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"if ($src1.new) memd($src3++#$offset) = $src2",
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[],
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"$src3 = $dst">,
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Requires<[HasV4T]>;
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// if (!Pv) memd(Rx++#s4:3)=Rtt
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// if (!Pv.new) memd(Rx++#s4:3)=Rtt
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let AddedComplexity = 10, neverHasSideEffects = 1,
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isPredicated = 1 in
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def POST_STdri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
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(ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3,
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s4_3Imm:$offset),
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"if (!$src1.new) memd($src3++#$offset) = $src2",
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[],
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"$src3 = $dst">,
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Requires<[HasV4T]>;
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//===----------------------------------------------------------------------===//
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// multiclass for store instructions with base + immediate offset
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// addressing mode and immediate stored value.
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// mem[bhw](Rx++#s4:3)=#s8
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// if ([!]Pv[.new]) mem[bhw](Rx++#s4:3)=#s6
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//===----------------------------------------------------------------------===//
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multiclass ST_Imm_Pbase<string mnemonic, Operand OffsetOp, bit isNot,
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bit isPredNew> {
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let PNewValue = !if(isPredNew, "new", "") in
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@ -1718,9 +1696,9 @@ multiclass ST_Imm<string mnemonic, string CextOp, Operand OffsetOp> {
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let addrMode = BaseImmOffset, InputType = "imm",
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validSubTargets = HasV4SubT in {
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defm STrib_imm : ST_Imm<"memb", "STrib", u6_0Imm>, ImmRegRel;
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defm STrih_imm : ST_Imm<"memh", "STrih", u6_1Imm>, ImmRegRel;
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defm STriw_imm : ST_Imm<"memw", "STriw", u6_2Imm>, ImmRegRel;
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defm STrib_imm : ST_Imm<"memb", "STrib", u6_0Imm>, ImmRegRel, PredNewRel;
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defm STrih_imm : ST_Imm<"memh", "STrih", u6_1Imm>, ImmRegRel, PredNewRel;
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defm STriw_imm : ST_Imm<"memw", "STriw", u6_2Imm>, ImmRegRel, PredNewRel;
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}
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let Predicates = [HasV4T], AddedComplexity = 10 in {
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@ -1757,30 +1735,6 @@ def STrib_shl_V4 : STInst<(outs),
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// memb(gp+#u16:0)=Rt
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// Store byte conditionally.
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// if ([!]Pv[.new]) memb(#u6)=Rt
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// if ([!]Pv[.new]) memb(Rx++#s4:0)=Rt
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// if (Pv) memb(Rx++#s4:0)=Rt
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// if (Pv.new) memb(Rx++#s4:0)=Rt
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let hasCtrlDep = 1,
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isPredicated = 1 in
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def POST_STbri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
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"if ($src1.new) memb($src3++#$offset) = $src2",
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[],"$src3 = $dst">,
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Requires<[HasV4T]>;
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// if (!Pv) memb(Rx++#s4:0)=Rt
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// if (!Pv.new) memb(Rx++#s4:0)=Rt
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let hasCtrlDep = 1,
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isPredicated = 1 in
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def POST_STbri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
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"if (!$src1.new) memb($src3++#$offset) = $src2",
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[],"$src3 = $dst">,
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Requires<[HasV4T]>;
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// Store halfword.
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// TODO: needs to be implemented
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// memh(Re=#U6)=Rt.H
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@ -1823,28 +1777,6 @@ def STrih_shl_V4 : STInst<(outs),
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// if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt.H
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// TODO: Needs to be implemented.
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// if ([!]Pv[.new]) memh(Rx++#s4:1)=Rt
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// if (Pv) memh(Rx++#s4:1)=Rt
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// if (Pv.new) memh(Rx++#s4:1)=Rt
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let hasCtrlDep = 1,
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isPredicated = 1 in
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def POST_SThri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
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"if ($src1.new) memh($src3++#$offset) = $src2",
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[],"$src3 = $dst">,
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Requires<[HasV4T]>;
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// if (!Pv) memh(Rx++#s4:1)=Rt
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// if (!Pv.new) memh(Rx++#s4:1)=Rt
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let hasCtrlDep = 1,
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isPredicated = 1 in
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def POST_SThri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
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"if (!$src1.new) memh($src3++#$offset) = $src2",
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[],"$src3 = $dst">,
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Requires<[HasV4T]>;
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// Store word.
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// memw(Re=#U6)=Rt
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// TODO: Needs to be implemented.
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@ -1879,29 +1811,6 @@ def STriw_shl_V4 : STInst<(outs),
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// memw(Rx++Mu:brev)=Rt
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// memw(gp+#u16:2)=Rt
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// if ([!]Pv[.new]) memw(Rx++#s4:2)=Rt
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// if (Pv) memw(Rx++#s4:2)=Rt
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// if (Pv.new) memw(Rx++#s4:2)=Rt
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let hasCtrlDep = 1,
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isPredicated = 1 in
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def POST_STwri_cdnPt_V4 : STInst2PI<(outs IntRegs:$dst),
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(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
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"if ($src1.new) memw($src3++#$offset) = $src2",
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[],"$src3 = $dst">,
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||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv) memw(Rx++#s4:2)=Rt
|
||||
// if (!Pv.new) memw(Rx++#s4:2)=Rt
|
||||
let hasCtrlDep = 1,
|
||||
isPredicated = 1 in
|
||||
def POST_STwri_cdnNotPt_V4 : STInst2PI<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
|
||||
"if (!$src1.new) memw($src3++#$offset) = $src2",
|
||||
[],"$src3 = $dst">,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
|
||||
/// store to global address
|
||||
|
||||
let isPredicable = 1, neverHasSideEffects = 1 in
|
||||
@ -2463,14 +2372,58 @@ def STrib_shl_nv_V4 : NVInst_V4<(outs),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// memb(Rx++#s4:0)=Nt.new
|
||||
let mayStore = 1, hasCtrlDep = 1, isPredicable = 1 in
|
||||
def POST_STbri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
|
||||
(ins IntRegs:$src1, IntRegs:$src2, s4_0Imm:$offset),
|
||||
"memb($src2++#$offset) = $src1.new",
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Post increment store
|
||||
// mem[bhwd](Rx++#s4:[0123])=Nt.new
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
multiclass ST_PostInc_Pbase_nv<string mnemonic, RegisterClass RC, Operand ImmOp,
|
||||
bit isNot, bit isPredNew> {
|
||||
let PNewValue = !if(isPredNew, "new", "") in
|
||||
def NAME#_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
|
||||
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
|
||||
") ")#mnemonic#"($src2++#$offset) = $src3.new",
|
||||
[],
|
||||
"$src2 = $dst">,
|
||||
Requires<[HasV4T]>;
|
||||
}
|
||||
|
||||
multiclass ST_PostInc_Pred_nv<string mnemonic, RegisterClass RC,
|
||||
Operand ImmOp, bit PredNot> {
|
||||
let PredSense = !if(PredNot, "false", "true") in {
|
||||
defm _c#NAME : ST_PostInc_Pbase_nv<mnemonic, RC, ImmOp, PredNot, 0>;
|
||||
// Predicate new
|
||||
let Predicates = [HasV4T], validSubTargets = HasV4SubT in
|
||||
defm _cdn#NAME : ST_PostInc_Pbase_nv<mnemonic, RC, ImmOp, PredNot, 1>;
|
||||
}
|
||||
}
|
||||
|
||||
let hasCtrlDep = 1, isNVStore = 1, neverHasSideEffects = 1 in
|
||||
multiclass ST_PostInc_nv<string mnemonic, string BaseOp, RegisterClass RC,
|
||||
Operand ImmOp> {
|
||||
|
||||
let BaseOpcode = "POST_"#BaseOp in {
|
||||
let isPredicable = 1 in
|
||||
def NAME#_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
|
||||
(ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
|
||||
mnemonic#"($src1++#$offset) = $src2.new",
|
||||
[],
|
||||
"$src1 = $dst">,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
let isPredicated = 1 in {
|
||||
defm Pt : ST_PostInc_Pred_nv<mnemonic, RC, ImmOp, 0 >;
|
||||
defm NotPt : ST_PostInc_Pred_nv<mnemonic, RC, ImmOp, 1 >;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
let validSubTargets = HasV4SubT in {
|
||||
defm POST_STbri: ST_PostInc_nv <"memb", "STrib", IntRegs, s4_0Imm>, AddrModeRel;
|
||||
defm POST_SThri: ST_PostInc_nv <"memh", "STrih", IntRegs, s4_1Imm>, AddrModeRel;
|
||||
defm POST_STwri: ST_PostInc_nv <"memw", "STriw", IntRegs, s4_2Imm>, AddrModeRel;
|
||||
}
|
||||
|
||||
// memb(Rx++#s4:0:circ(Mu))=Nt.new
|
||||
// memb(Rx++I:circ(Mu))=Nt.new
|
||||
@ -2493,43 +2446,6 @@ def STb_GP_nv_V4 : NVInst_V4<(outs),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if ([!]Pv[.new]) memb(Rx++#s4:0)=Nt.new
|
||||
// if (Pv) memb(Rx++#s4:0)=Nt.new
|
||||
let mayStore = 1, hasCtrlDep = 1,
|
||||
isPredicated = 1 in
|
||||
def POST_STbri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
|
||||
"if ($src1) memb($src3++#$offset) = $src2.new",
|
||||
[],"$src3 = $dst">,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (Pv.new) memb(Rx++#s4:0)=Nt.new
|
||||
let mayStore = 1, hasCtrlDep = 1,
|
||||
isPredicated = 1 in
|
||||
def POST_STbri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
|
||||
"if ($src1.new) memb($src3++#$offset) = $src2.new",
|
||||
[],"$src3 = $dst">,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv) memb(Rx++#s4:0)=Nt.new
|
||||
let mayStore = 1, hasCtrlDep = 1,
|
||||
isPredicated = 1 in
|
||||
def POST_STbri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
|
||||
"if (!$src1) memb($src3++#$offset) = $src2.new",
|
||||
[],"$src3 = $dst">,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv.new) memb(Rx++#s4:0)=Nt.new
|
||||
let mayStore = 1, hasCtrlDep = 1,
|
||||
isPredicated = 1 in
|
||||
def POST_STbri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset),
|
||||
"if (!$src1.new) memb($src3++#$offset) = $src2.new",
|
||||
[],"$src3 = $dst">,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// memh(Ru<<#u2+#U6)=Nt.new
|
||||
let mayStore = 1, AddedComplexity = 10 in
|
||||
def STrih_shl_nv_V4 : NVInst_V4<(outs),
|
||||
@ -2538,15 +2454,6 @@ def STrih_shl_nv_V4 : NVInst_V4<(outs),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// memh(Rx++#s4:1)=Nt.new
|
||||
let mayStore = 1, hasCtrlDep = 1, isPredicable = 1 in
|
||||
def POST_SThri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
|
||||
(ins IntRegs:$src1, IntRegs:$src2, s4_1Imm:$offset),
|
||||
"memh($src2++#$offset) = $src1.new",
|
||||
[],
|
||||
"$src2 = $dst">,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// memh(Rx++#s4:1:circ(Mu))=Nt.new
|
||||
// memh(Rx++I:circ(Mu))=Nt.new
|
||||
// memh(Rx++Mu)=Nt.new
|
||||
@ -2568,44 +2475,6 @@ def STh_GP_nv_V4 : NVInst_V4<(outs),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
|
||||
// if ([!]Pv[]) memh(Rx++#s4:1)=Nt.new
|
||||
// if (Pv) memh(Rx++#s4:1)=Nt.new
|
||||
let mayStore = 1, hasCtrlDep = 1,
|
||||
isPredicated = 1 in
|
||||
def POST_SThri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
|
||||
"if ($src1) memh($src3++#$offset) = $src2.new",
|
||||
[],"$src3 = $dst">,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (Pv.new) memh(Rx++#s4:1)=Nt.new
|
||||
let mayStore = 1, hasCtrlDep = 1,
|
||||
isPredicated = 1 in
|
||||
def POST_SThri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
|
||||
"if ($src1.new) memh($src3++#$offset) = $src2.new",
|
||||
[],"$src3 = $dst">,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv) memh(Rx++#s4:1)=Nt.new
|
||||
let mayStore = 1, hasCtrlDep = 1,
|
||||
isPredicated = 1 in
|
||||
def POST_SThri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
|
||||
"if (!$src1) memh($src3++#$offset) = $src2.new",
|
||||
[],"$src3 = $dst">,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv.new) memh(Rx++#s4:1)=Nt.new
|
||||
let mayStore = 1, hasCtrlDep = 1,
|
||||
isPredicated = 1 in
|
||||
def POST_SThri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset),
|
||||
"if (!$src1.new) memh($src3++#$offset) = $src2.new",
|
||||
[],"$src3 = $dst">,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// memw(Ru<<#u2+#U6)=Nt.new
|
||||
let mayStore = 1, AddedComplexity = 10 in
|
||||
def STriw_shl_nv_V4 : NVInst_V4<(outs),
|
||||
@ -2614,15 +2483,6 @@ def STriw_shl_nv_V4 : NVInst_V4<(outs),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// memw(Rx++#s4:2)=Nt.new
|
||||
let mayStore = 1, hasCtrlDep = 1, isPredicable = 1 in
|
||||
def POST_STwri_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
|
||||
(ins IntRegs:$src1, IntRegs:$src2, s4_2Imm:$offset),
|
||||
"memw($src2++#$offset) = $src1.new",
|
||||
[],
|
||||
"$src2 = $dst">,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// memw(Rx++#s4:2:circ(Mu))=Nt.new
|
||||
// memw(Rx++I:circ(Mu))=Nt.new
|
||||
// memw(Rx++Mu)=Nt.new
|
||||
@ -2642,45 +2502,6 @@ def STw_GP_nv_V4 : NVInst_V4<(outs),
|
||||
[]>,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if ([!]Pv[.new]) memw(Rx++#s4:2)=Nt.new
|
||||
// if (Pv) memw(Rx++#s4:2)=Nt.new
|
||||
let mayStore = 1, hasCtrlDep = 1,
|
||||
isPredicated = 1 in
|
||||
def POST_STwri_cPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
|
||||
"if ($src1) memw($src3++#$offset) = $src2.new",
|
||||
[],"$src3 = $dst">,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (Pv.new) memw(Rx++#s4:2)=Nt.new
|
||||
let mayStore = 1, hasCtrlDep = 1,
|
||||
isPredicated = 1 in
|
||||
def POST_STwri_cdnPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
|
||||
"if ($src1.new) memw($src3++#$offset) = $src2.new",
|
||||
[],"$src3 = $dst">,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv) memw(Rx++#s4:2)=Nt.new
|
||||
let mayStore = 1, hasCtrlDep = 1,
|
||||
isPredicated = 1 in
|
||||
def POST_STwri_cNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
|
||||
"if (!$src1) memw($src3++#$offset) = $src2.new",
|
||||
[],"$src3 = $dst">,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
// if (!Pv.new) memw(Rx++#s4:2)=Nt.new
|
||||
let mayStore = 1, hasCtrlDep = 1,
|
||||
isPredicated = 1 in
|
||||
def POST_STwri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset),
|
||||
"if (!$src1.new) memw($src3++#$offset) = $src2.new",
|
||||
[],"$src3 = $dst">,
|
||||
Requires<[HasV4T]>;
|
||||
|
||||
|
||||
|
||||
// if (Pv) memb(##global) = Rt
|
||||
let mayStore = 1, neverHasSideEffects = 1 in
|
||||
def STb_GP_cPt_nv_V4 : NVInst_V4<(outs),
|
||||
|
||||
Loading…
Reference in New Issue
Block a user