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Now that RegistersDefinedFromSameValue handles one instruction being an

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implicit_def, the other instruction can be anything, including instructions
that define multiple values. Be careful about that and don't assume what operand
0 is.
Fixes pr13249.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159509 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2012-07-01 17:08:01 +00:00
parent 8f40f7b867
commit 9c3d5a70f4
2 changed files with 31 additions and 14 deletions
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18
lib/CodeGen/RegisterCoalescer.cpp
View File

@ -1175,28 +1175,18 @@ static bool RegistersDefinedFromSameValue(LiveIntervals &li,
if (!MI || CP.isPartial() || CP.isPhys())
return false;
unsigned Dst = MI->getOperand(0).getReg();
if (!TargetRegisterInfo::isVirtualRegister(Dst))
unsigned A = CP.getDstReg();
if (!TargetRegisterInfo::isVirtualRegister(A))
return false;
unsigned A = CP.getDstReg();
unsigned B = CP.getSrcReg();
if (B == Dst)
std::swap(A, B);
assert(Dst == A);
if (!TargetRegisterInfo::isVirtualRegister(B))
return false;
MachineInstr *OtherMI = li.getInstructionFromIndex(OtherVNI->def);
if (!OtherMI)
return false;
unsigned OtherDst = OtherMI->getOperand(0).getReg();
if (!TargetRegisterInfo::isVirtualRegister(OtherDst))
return false;
assert(OtherDst == B);
if (MI->isImplicitDef()) {
DupCopies.push_back(MI);
return true;

27
test/CodeGen/ARM/pr13249.ll Normal file
View File

@ -0,0 +1,27 @@
; RUN: llc < %s -mtriple armv7--linux-gnueabi
define arm_aapcscc i8* @__strtok_r_1c(i8* %arg, i8 signext %arg1, i8** nocapture %arg2) nounwind {
bb:
br label %bb3
bb3: ; preds = %bb3, %bb
%tmp = phi i8* [ %tmp5, %bb3 ], [ %arg, %bb ]
%tmp4 = load i8* %tmp, align 1
%tmp5 = getelementptr inbounds i8* %tmp, i32 1
br i1 undef, label %bb3, label %bb7
bb7: ; preds = %bb13, %bb3
%tmp8 = phi i8 [ %tmp14, %bb13 ], [ %tmp4, %bb3 ]
%tmp9 = phi i8* [ %tmp12, %bb13 ], [ %tmp, %bb3 ]
%tmp10 = icmp ne i8 %tmp8, %arg1
%tmp12 = getelementptr inbounds i8* %tmp9, i32 1
br i1 %tmp10, label %bb13, label %bb15
bb13: ; preds = %bb7
%tmp14 = load i8* %tmp12, align 1
br label %bb7
bb15: ; preds = %bb7
store i8* %tmp9, i8** %arg2, align 4
ret i8* %tmp
}