mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-21 18:29:46 +00:00
Updates to the ARM target assembler for llvm-mc per review comments from
Daniel Dunbar. - Reordered the fields in the ARMOperand Mem struct to make the struct smaller. Making bool's into 1 bit fields and put the MCExpr* fields adjacent to each other. - Fixed a number of places in ARMAsmParser.cpp so they have doxygen comments. - Change the name of ARMAsmParser::ParseRegister() to MaybeParseRegister and added the bool ParseWriteBack parameter. - Changed ARMAsmParser::ParseMemory() to call MaybeParseRegister(). - Added ARMAsmParser::ParseMemoryOffsetReg to factor out parsing the offset of a memory operand. And use it for both parsing both preindexed and post indexing addressing forms in ARMAsmParser::ParseMemory. - Changed the first argument to ParseShift() to a reference. - Changed ParseShift() to check for Rrx first and return to reduce nesting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85632 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -44,13 +44,21 @@ private:
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bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
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bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
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bool ParseRegister(ARMOperand &Op);
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bool MaybeParseRegister(ARMOperand &Op, bool ParseWriteBack);
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bool ParseRegisterList(ARMOperand &Op);
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bool ParseRegisterList(ARMOperand &Op);
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bool ParseMemory(ARMOperand &Op);
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bool ParseMemory(ARMOperand &Op);
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bool ParseShift(enum ShiftType *St, const MCExpr *&ShiftAmount);
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bool ParseMemoryOffsetReg(bool &Negative,
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bool &OffsetRegShifted,
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enum ShiftType &ShiftType,
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const MCExpr *&ShiftAmount,
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const MCExpr *&Offset,
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bool &OffsetIsReg,
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int OffsetRegNum);
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bool ParseShift(enum ShiftType &St, const MCExpr *&ShiftAmount);
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bool ParseOperand(ARMOperand &Op);
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bool ParseOperand(ARMOperand &Op);
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@ -123,16 +131,17 @@ struct ARMOperand {
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// This is for all forms of ARM address expressions
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// This is for all forms of ARM address expressions
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struct {
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struct {
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unsigned BaseRegNum;
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unsigned BaseRegNum;
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bool OffsetIsReg;
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const MCExpr *Offset; // used when OffsetIsReg is false
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unsigned OffsetRegNum; // used when OffsetIsReg is true
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unsigned OffsetRegNum; // used when OffsetIsReg is true
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bool OffsetRegShifted; // only used when OffsetIsReg is true
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const MCExpr *Offset; // used when OffsetIsReg is false
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enum ShiftType ShiftType; // used when OffsetRegShifted is true
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const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
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const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
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bool Preindexed;
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enum ShiftType ShiftType; // used when OffsetRegShifted is true
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bool Postindexed;
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unsigned
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bool Negative; // only used when OffsetIsReg is true
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OffsetRegShifted : 1, // only used when OffsetIsReg is true
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bool Writeback;
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Preindexed : 1,
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Postindexed : 1,
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OffsetIsReg : 1,
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Negative : 1, // only used when OffsetIsReg is true
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Writeback : 1;
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} Mem;
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} Mem;
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};
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};
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@ -208,12 +217,12 @@ struct ARMOperand {
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} // end anonymous namespace.
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} // end anonymous namespace.
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// Try to parse a register name. The token must be an Identifier when called,
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/// Try to parse a register name. The token must be an Identifier when called,
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// and if it is a register name a Reg operand is created, the token is eaten
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/// and if it is a register name a Reg operand is created, the token is eaten
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// and false is returned. Else true is returned and no token is eaten.
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/// and false is returned. Else true is returned and no token is eaten.
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// TODO this is likely to change to allow different register types and or to
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/// TODO this is likely to change to allow different register types and or to
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// parse for a specific register type.
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/// parse for a specific register type.
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bool ARMAsmParser::ParseRegister(ARMOperand &Op) {
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bool ARMAsmParser::MaybeParseRegister(ARMOperand &Op, bool ParseWriteBack) {
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const AsmToken &Tok = getLexer().getTok();
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const AsmToken &Tok = getLexer().getTok();
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assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
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assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
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@ -227,10 +236,12 @@ bool ARMAsmParser::ParseRegister(ARMOperand &Op) {
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getLexer().Lex(); // Eat identifier token.
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getLexer().Lex(); // Eat identifier token.
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bool Writeback = false;
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bool Writeback = false;
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const AsmToken &ExclaimTok = getLexer().getTok();
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if (ParseWriteBack) {
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if (ExclaimTok.is(AsmToken::Exclaim)) {
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const AsmToken &ExclaimTok = getLexer().getTok();
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Writeback = true;
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if (ExclaimTok.is(AsmToken::Exclaim)) {
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getLexer().Lex(); // Eat exclaim token
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Writeback = true;
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getLexer().Lex(); // Eat exclaim token
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}
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}
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}
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Op = ARMOperand::CreateReg(RegNum, Writeback);
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Op = ARMOperand::CreateReg(RegNum, Writeback);
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@ -238,8 +249,8 @@ bool ARMAsmParser::ParseRegister(ARMOperand &Op) {
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return false;
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return false;
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}
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}
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// Parse a register list, return false if successful else return true or an
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/// Parse a register list, return false if successful else return true or an
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// error. The first token must be a '{' when called.
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/// error. The first token must be a '{' when called.
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bool ARMAsmParser::ParseRegisterList(ARMOperand &Op) {
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bool ARMAsmParser::ParseRegisterList(ARMOperand &Op) {
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assert(getLexer().getTok().is(AsmToken::LCurly) &&
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assert(getLexer().getTok().is(AsmToken::LCurly) &&
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"Token is not an Left Curly Brace");
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"Token is not an Left Curly Brace");
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@ -285,10 +296,10 @@ bool ARMAsmParser::ParseRegisterList(ARMOperand &Op) {
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return false;
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return false;
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}
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}
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// Parse an arm memory expression, return false if successful else return true
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/// Parse an arm memory expression, return false if successful else return true
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// or an error. The first token must be a '[' when called.
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/// or an error. The first token must be a '[' when called.
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// TODO Only preindexing and postindexing addressing are started, unindexed
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/// TODO Only preindexing and postindexing addressing are started, unindexed
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// with option, etc are still to do.
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/// with option, etc are still to do.
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bool ARMAsmParser::ParseMemory(ARMOperand &Op) {
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bool ARMAsmParser::ParseMemory(ARMOperand &Op) {
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assert(getLexer().getTok().is(AsmToken::LBrac) &&
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assert(getLexer().getTok().is(AsmToken::LBrac) &&
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"Token is not an Left Bracket");
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"Token is not an Left Bracket");
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@ -297,10 +308,9 @@ bool ARMAsmParser::ParseMemory(ARMOperand &Op) {
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const AsmToken &BaseRegTok = getLexer().getTok();
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const AsmToken &BaseRegTok = getLexer().getTok();
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if (BaseRegTok.isNot(AsmToken::Identifier))
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if (BaseRegTok.isNot(AsmToken::Identifier))
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return Error(BaseRegTok.getLoc(), "register expected");
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return Error(BaseRegTok.getLoc(), "register expected");
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int BaseRegNum = MatchRegisterName(BaseRegTok.getString());
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if (MaybeParseRegister(Op, false))
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if (BaseRegNum == -1)
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return Error(BaseRegTok.getLoc(), "register expected");
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return Error(BaseRegTok.getLoc(), "register expected");
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getLexer().Lex(); // Eat identifier token.
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int BaseRegNum = Op.getReg();
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bool Preindexed = false;
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bool Preindexed = false;
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bool Postindexed = false;
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bool Postindexed = false;
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@ -308,55 +318,20 @@ bool ARMAsmParser::ParseMemory(ARMOperand &Op) {
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bool Negative = false;
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bool Negative = false;
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bool Writeback = false;
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bool Writeback = false;
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// First look for preindexed address forms:
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// First look for preindexed address forms, that is after the "[Rn" we now
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// [Rn, +/-Rm]
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// have to see if the next token is a comma.
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// [Rn, #offset]
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// [Rn, +/-Rm, shift]
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// that is after the "[Rn" we now have see if the next token is a comma.
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const AsmToken &Tok = getLexer().getTok();
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const AsmToken &Tok = getLexer().getTok();
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if (Tok.is(AsmToken::Comma)) {
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if (Tok.is(AsmToken::Comma)) {
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Preindexed = true;
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Preindexed = true;
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getLexer().Lex(); // Eat comma token.
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getLexer().Lex(); // Eat comma token.
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int OffsetRegNum;
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const AsmToken &NextTok = getLexer().getTok();
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bool OffsetRegShifted;
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if (NextTok.is(AsmToken::Plus))
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getLexer().Lex(); // Eat plus token.
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else if (NextTok.is(AsmToken::Minus)) {
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Negative = true;
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getLexer().Lex(); // Eat minus token
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}
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// See if there is a register following the "[Rn," we have so far.
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const AsmToken &OffsetRegTok = getLexer().getTok();
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int OffsetRegNum = MatchRegisterName(OffsetRegTok.getString());
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bool OffsetRegShifted = false;
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enum ShiftType ShiftType;
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enum ShiftType ShiftType;
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const MCExpr *ShiftAmount;
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const MCExpr *ShiftAmount;
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const MCExpr *Offset;
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const MCExpr *Offset;
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if (OffsetRegNum != -1) {
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if(ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
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OffsetIsReg = true;
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Offset, OffsetIsReg, OffsetRegNum))
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getLexer().Lex(); // Eat identifier token for the offset register.
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return true;
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// Look for a comma then a shift
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const AsmToken &Tok = getLexer().getTok();
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if (Tok.is(AsmToken::Comma)) {
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getLexer().Lex(); // Eat comma token.
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const AsmToken &Tok = getLexer().getTok();
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if (ParseShift(&ShiftType, ShiftAmount))
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return Error(Tok.getLoc(), "shift expected");
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OffsetRegShifted = true;
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}
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}
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else { // "[Rn," we have so far was not followed by "Rm"
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// Look for #offset following the "[Rn,"
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const AsmToken &HashTok = getLexer().getTok();
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if (HashTok.isNot(AsmToken::Hash))
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return Error(HashTok.getLoc(), "'#' expected");
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getLexer().Lex(); // Eat hash token.
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if (getParser().ParseExpression(Offset))
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return true;
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}
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const AsmToken &RBracTok = getLexer().getTok();
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const AsmToken &RBracTok = getLexer().getTok();
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if (RBracTok.isNot(AsmToken::RBrac))
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if (RBracTok.isNot(AsmToken::RBrac))
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return Error(RBracTok.getLoc(), "']' expected");
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return Error(RBracTok.getLoc(), "']' expected");
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@ -374,11 +349,8 @@ bool ARMAsmParser::ParseMemory(ARMOperand &Op) {
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}
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}
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// The "[Rn" we have so far was not followed by a comma.
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// The "[Rn" we have so far was not followed by a comma.
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else if (Tok.is(AsmToken::RBrac)) {
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else if (Tok.is(AsmToken::RBrac)) {
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// This is a post indexing addressing forms:
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// This is a post indexing addressing forms, that is a ']' follows after
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// [Rn], #offset
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// the "[Rn".
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// [Rn], +/-Rm
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// [Rn], +/-Rm, shift
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// that is a ']' follows after the "[Rn".
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Postindexed = true;
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Postindexed = true;
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Writeback = true;
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Writeback = true;
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getLexer().Lex(); // Eat right bracket token.
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getLexer().Lex(); // Eat right bracket token.
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@ -394,42 +366,9 @@ bool ARMAsmParser::ParseMemory(ARMOperand &Op) {
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if (NextTok.isNot(AsmToken::Comma))
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if (NextTok.isNot(AsmToken::Comma))
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return Error(NextTok.getLoc(), "',' expected");
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return Error(NextTok.getLoc(), "',' expected");
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getLexer().Lex(); // Eat comma token.
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getLexer().Lex(); // Eat comma token.
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if(ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
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const AsmToken &PlusMinusTok = getLexer().getTok();
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ShiftAmount, Offset, OffsetIsReg, OffsetRegNum))
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if (PlusMinusTok.is(AsmToken::Plus))
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return true;
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getLexer().Lex(); // Eat plus token.
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else if (PlusMinusTok.is(AsmToken::Minus)) {
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Negative = true;
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getLexer().Lex(); // Eat minus token
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}
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// See if there is a register following the "[Rn]," we have so far.
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const AsmToken &OffsetRegTok = getLexer().getTok();
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OffsetRegNum = MatchRegisterName(OffsetRegTok.getString());
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if (OffsetRegNum != -1) {
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OffsetIsReg = true;
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getLexer().Lex(); // Eat identifier token for the offset register.
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// Look for a comma then a shift
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const AsmToken &Tok = getLexer().getTok();
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if (Tok.is(AsmToken::Comma)) {
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getLexer().Lex(); // Eat comma token.
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const AsmToken &Tok = getLexer().getTok();
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if (ParseShift(&ShiftType, ShiftAmount))
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return Error(Tok.getLoc(), "shift expected");
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OffsetRegShifted = true;
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}
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}
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else { // "[Rn]," we have so far was not followed by "Rm"
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// Look for #offset following the "[Rn],"
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const AsmToken &HashTok = getLexer().getTok();
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if (HashTok.isNot(AsmToken::Hash))
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return Error(HashTok.getLoc(), "'#' expected");
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getLexer().Lex(); // Eat hash token.
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if (getParser().ParseExpression(Offset))
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return true;
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}
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}
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}
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Op = ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
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Op = ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
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@ -441,45 +380,105 @@ bool ARMAsmParser::ParseMemory(ARMOperand &Op) {
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return true;
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return true;
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}
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}
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/// ParseShift as one of these two:
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/// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
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/// ( lsl | lsr | asr | ror ) , # shift_amount
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/// we will parse the following (were +/- means that a plus or minus is
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/// rrx
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/// optional):
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/// and returns true if it parses a shift otherwise it returns false.
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/// +/-Rm
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bool ARMAsmParser::ParseShift(ShiftType *St, const MCExpr *&ShiftAmount) {
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/// +/-Rm, shift
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const AsmToken &Tok = getLexer().getTok();
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/// #offset
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if (Tok.isNot(AsmToken::Identifier))
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/// we return false on success or an error otherwise.
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return true;
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bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
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const StringRef &ShiftName = Tok.getString();
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bool &OffsetRegShifted,
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if (ShiftName == "lsl" || ShiftName == "LSL")
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enum ShiftType &ShiftType,
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*St = Lsl;
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const MCExpr *&ShiftAmount,
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else if (ShiftName == "lsr" || ShiftName == "LSR")
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const MCExpr *&Offset,
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*St = Lsr;
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bool &OffsetIsReg,
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else if (ShiftName == "asr" || ShiftName == "ASR")
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int OffsetRegNum) {
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*St = Asr;
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ARMOperand Op;
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else if (ShiftName == "ror" || ShiftName == "ROR")
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Negative = false;
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*St = Ror;
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OffsetRegShifted = false;
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else if (ShiftName == "rrx" || ShiftName == "RRX")
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OffsetIsReg = false;
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*St = Rrx;
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OffsetRegNum = -1;
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else
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const AsmToken &NextTok = getLexer().getTok();
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return true;
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if (NextTok.is(AsmToken::Plus))
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getLexer().Lex(); // Eat shift type token.
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getLexer().Lex(); // Eat plus token.
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else if (NextTok.is(AsmToken::Minus)) {
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Negative = true;
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getLexer().Lex(); // Eat minus token
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}
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// See if there is a register following the "[Rn," or "[Rn]," we have so far.
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const AsmToken &OffsetRegTok = getLexer().getTok();
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if (OffsetRegTok.is(AsmToken::Identifier)) {
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OffsetIsReg = !MaybeParseRegister(Op, false);
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if (OffsetIsReg)
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OffsetRegNum = Op.getReg();
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}
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// If we parsed a register as the offset then their can be a shift after that
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if (OffsetRegNum != -1) {
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// Look for a comma then a shift
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const AsmToken &Tok = getLexer().getTok();
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if (Tok.is(AsmToken::Comma)) {
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getLexer().Lex(); // Eat comma token.
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// For all but a Rotate right there must be a '#' and a shift amount
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const AsmToken &Tok = getLexer().getTok();
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if (*St != Rrx) {
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if (ParseShift(ShiftType, ShiftAmount))
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// Look for # following the shift type
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return Error(Tok.getLoc(), "shift expected");
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OffsetRegShifted = true;
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}
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}
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else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
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// Look for #offset following the "[Rn," or "[Rn],"
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const AsmToken &HashTok = getLexer().getTok();
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const AsmToken &HashTok = getLexer().getTok();
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if (HashTok.isNot(AsmToken::Hash))
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if (HashTok.isNot(AsmToken::Hash))
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return Error(HashTok.getLoc(), "'#' expected");
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return Error(HashTok.getLoc(), "'#' expected");
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getLexer().Lex(); // Eat hash token.
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getLexer().Lex(); // Eat hash token.
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if (getParser().ParseExpression(ShiftAmount))
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if (getParser().ParseExpression(Offset))
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return true;
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return true;
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}
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}
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return false;
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}
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/// ParseShift as one of these two:
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||||||
|
/// ( lsl | lsr | asr | ror ) , # shift_amount
|
||||||
|
/// rrx
|
||||||
|
/// and returns true if it parses a shift otherwise it returns false.
|
||||||
|
bool ARMAsmParser::ParseShift(ShiftType &St, const MCExpr *&ShiftAmount) {
|
||||||
|
const AsmToken &Tok = getLexer().getTok();
|
||||||
|
if (Tok.isNot(AsmToken::Identifier))
|
||||||
|
return true;
|
||||||
|
const StringRef &ShiftName = Tok.getString();
|
||||||
|
if (ShiftName == "lsl" || ShiftName == "LSL")
|
||||||
|
St = Lsl;
|
||||||
|
else if (ShiftName == "lsr" || ShiftName == "LSR")
|
||||||
|
St = Lsr;
|
||||||
|
else if (ShiftName == "asr" || ShiftName == "ASR")
|
||||||
|
St = Asr;
|
||||||
|
else if (ShiftName == "ror" || ShiftName == "ROR")
|
||||||
|
St = Ror;
|
||||||
|
else if (ShiftName == "rrx" || ShiftName == "RRX")
|
||||||
|
St = Rrx;
|
||||||
|
else
|
||||||
|
return true;
|
||||||
|
getLexer().Lex(); // Eat shift type token.
|
||||||
|
|
||||||
|
// Rrx stands alone.
|
||||||
|
if (St == Rrx)
|
||||||
|
return false;
|
||||||
|
|
||||||
|
// Otherwise, there must be a '#' and a shift amount.
|
||||||
|
const AsmToken &HashTok = getLexer().getTok();
|
||||||
|
if (HashTok.isNot(AsmToken::Hash))
|
||||||
|
return Error(HashTok.getLoc(), "'#' expected");
|
||||||
|
getLexer().Lex(); // Eat hash token.
|
||||||
|
|
||||||
|
if (getParser().ParseExpression(ShiftAmount))
|
||||||
|
return true;
|
||||||
|
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
// A hack to allow some testing, to be replaced by a real table gen version.
|
/// A hack to allow some testing, to be replaced by a real table gen version.
|
||||||
int ARMAsmParser::MatchRegisterName(const StringRef &Name) {
|
int ARMAsmParser::MatchRegisterName(const StringRef &Name) {
|
||||||
if (Name == "r0" || Name == "R0")
|
if (Name == "r0" || Name == "R0")
|
||||||
return 0;
|
return 0;
|
||||||
@ -518,7 +517,7 @@ int ARMAsmParser::MatchRegisterName(const StringRef &Name) {
|
|||||||
return -1;
|
return -1;
|
||||||
}
|
}
|
||||||
|
|
||||||
// A hack to allow some testing, to be replaced by a real table gen version.
|
/// A hack to allow some testing, to be replaced by a real table gen version.
|
||||||
bool ARMAsmParser::MatchInstruction(SmallVectorImpl<ARMOperand> &Operands,
|
bool ARMAsmParser::MatchInstruction(SmallVectorImpl<ARMOperand> &Operands,
|
||||||
MCInst &Inst) {
|
MCInst &Inst) {
|
||||||
struct ARMOperand Op0 = Operands[0];
|
struct ARMOperand Op0 = Operands[0];
|
||||||
@ -549,12 +548,12 @@ bool ARMAsmParser::MatchInstruction(SmallVectorImpl<ARMOperand> &Operands,
|
|||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
// Parse a arm instruction operand. For now this parses the operand regardless
|
/// Parse a arm instruction operand. For now this parses the operand regardless
|
||||||
// of the mnemonic.
|
/// of the mnemonic.
|
||||||
bool ARMAsmParser::ParseOperand(ARMOperand &Op) {
|
bool ARMAsmParser::ParseOperand(ARMOperand &Op) {
|
||||||
switch (getLexer().getKind()) {
|
switch (getLexer().getKind()) {
|
||||||
case AsmToken::Identifier:
|
case AsmToken::Identifier:
|
||||||
if (!ParseRegister(Op))
|
if (!MaybeParseRegister(Op, true))
|
||||||
return false;
|
return false;
|
||||||
// This was not a register so parse other operands that start with an
|
// This was not a register so parse other operands that start with an
|
||||||
// identifier (like labels) as expressions and create them as immediates.
|
// identifier (like labels) as expressions and create them as immediates.
|
||||||
@ -581,7 +580,7 @@ bool ARMAsmParser::ParseOperand(ARMOperand &Op) {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
// Parse an arm instruction mnemonic followed by its operands.
|
/// Parse an arm instruction mnemonic followed by its operands.
|
||||||
bool ARMAsmParser::ParseInstruction(const StringRef &Name, MCInst &Inst) {
|
bool ARMAsmParser::ParseInstruction(const StringRef &Name, MCInst &Inst) {
|
||||||
SmallVector<ARMOperand, 7> Operands;
|
SmallVector<ARMOperand, 7> Operands;
|
||||||
|
|
||||||
@ -739,7 +738,7 @@ bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
|
|||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
// Force static initialization.
|
/// Force static initialization.
|
||||||
extern "C" void LLVMInitializeARMAsmParser() {
|
extern "C" void LLVMInitializeARMAsmParser() {
|
||||||
RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
|
RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
|
||||||
RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
|
RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
|
||||||
|
Loading…
Reference in New Issue
Block a user