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Implement 'e' and 'f' modifiers for Neon inline asm. <rdar://problem/10551006>
These modifiers simply select either the low or high D subregister of a Neon Q register. I've also removed the unimplemented 'p' modifier, which turns out to be a bit different than the comment here suggests and as far as I can tell was only intended for internal use in Apple's version of gcc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146417 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -493,11 +493,21 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
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return false;
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}
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// These modifiers are not yet supported.
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case 'p': // The high single-precision register of a VFP double-precision
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// register.
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case 'e': // The low doubleword register of a NEON quad register.
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case 'f': // The high doubleword register of a NEON quad register.
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case 'f': { // The high doubleword register of a NEON quad register.
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if (!MI->getOperand(OpNum).isReg())
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return true;
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unsigned Reg = MI->getOperand(OpNum).getReg();
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if (!ARM::QPRRegClass.contains(Reg))
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return true;
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const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
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unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
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ARM::dsub_0 : ARM::dsub_1);
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O << ARMInstPrinter::getRegisterName(SubReg);
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return false;
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}
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// These modifiers are not yet supported.
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case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
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case 'H': // The highest-numbered register of a pair.
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return true;
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@ -110,3 +110,13 @@ entry:
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call void asm "str $1, $0", "=*Q,r"(i8** %f.addr, i32 %g) nounwind
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ret void
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}
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; Radar 10551006
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define <4 x i32> @t11(i32* %p) nounwind {
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entry:
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; CHECK: t11
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; CHECK: vld1.s32 {d16[], d17[]}, [r0]
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%0 = tail call <4 x i32> asm "vld1.s32 {${0:e}[], ${0:f}[]}, [$1]", "=w,r"(i32* %p) nounwind
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ret <4 x i32> %0
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}
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