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Re-apply r237247 - [AArch64] Codegen VMAX/VMIN for safe math cases
No longer breaks SPEC2000/2006 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237361 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -491,6 +491,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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setTargetDAGCombine(ISD::SELECT);
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setTargetDAGCombine(ISD::VSELECT);
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setTargetDAGCombine(ISD::SELECT_CC);
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setTargetDAGCombine(ISD::INTRINSIC_VOID);
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setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
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@ -3567,7 +3568,8 @@ SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
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/// operations would *not* be semantically equivalent.
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static bool selectCCOpsAreFMaxCompatible(SDValue Cmp, SDValue Result) {
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if (Cmp == Result)
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return true;
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return (Cmp.getValueType() == MVT::f32 ||
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Cmp.getValueType() == MVT::f64);
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ConstantFPSDNode *CCmp = dyn_cast<ConstantFPSDNode>(Cmp);
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ConstantFPSDNode *CResult = dyn_cast<ConstantFPSDNode>(Result);
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@ -3701,46 +3703,6 @@ SDValue AArch64TargetLowering::LowerSELECT_CC(ISD::CondCode CC, SDValue LHS,
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assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
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assert(LHS.getValueType() == RHS.getValueType());
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EVT VT = TVal.getValueType();
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// Try to match this select into a max/min operation, which have dedicated
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// opcode in the instruction set.
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// FIXME: This is not correct in the presence of NaNs, so we only enable this
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// in no-NaNs mode.
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if (getTargetMachine().Options.NoNaNsFPMath) {
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SDValue MinMaxLHS = TVal, MinMaxRHS = FVal;
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if (selectCCOpsAreFMaxCompatible(LHS, MinMaxRHS) &&
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selectCCOpsAreFMaxCompatible(RHS, MinMaxLHS)) {
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CC = ISD::getSetCCSwappedOperands(CC);
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std::swap(MinMaxLHS, MinMaxRHS);
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}
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if (selectCCOpsAreFMaxCompatible(LHS, MinMaxLHS) &&
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selectCCOpsAreFMaxCompatible(RHS, MinMaxRHS)) {
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switch (CC) {
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default:
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break;
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case ISD::SETGT:
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case ISD::SETGE:
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case ISD::SETUGT:
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case ISD::SETUGE:
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case ISD::SETOGT:
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case ISD::SETOGE:
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return DAG.getNode(AArch64ISD::FMAX, dl, VT, MinMaxLHS, MinMaxRHS);
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break;
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case ISD::SETLT:
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case ISD::SETLE:
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case ISD::SETULT:
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case ISD::SETULE:
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case ISD::SETOLT:
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case ISD::SETOLE:
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return DAG.getNode(AArch64ISD::FMIN, dl, VT, MinMaxLHS, MinMaxRHS);
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break;
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}
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}
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}
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// If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
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// and do the comparison.
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SDValue Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
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// Unfortunately, the mapping of LLVM FP CC's onto AArch64 CC's isn't totally
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@ -8735,6 +8697,75 @@ static SDValue performSelectCombine(SDNode *N,
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return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2));
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}
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/// performSelectCCCombine - Target-specific DAG combining for ISD::SELECT_CC
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/// to match FMIN/FMAX patterns.
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static SDValue performSelectCCCombine(SDNode *N, SelectionDAG &DAG) {
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// Try to use FMIN/FMAX instructions for FP selects like "x < y ? x : y".
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// Unless the NoNaNsFPMath option is set, be careful about NaNs:
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// vmax/vmin return NaN if either operand is a NaN;
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// only do the transformation when it matches that behavior.
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SDValue CondLHS = N->getOperand(0);
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SDValue CondRHS = N->getOperand(1);
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SDValue LHS = N->getOperand(2);
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SDValue RHS = N->getOperand(3);
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ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
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unsigned Opcode;
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bool IsReversed;
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if (selectCCOpsAreFMaxCompatible(CondLHS, LHS) &&
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selectCCOpsAreFMaxCompatible(CondRHS, RHS)) {
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IsReversed = false; // x CC y ? x : y
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} else if (selectCCOpsAreFMaxCompatible(CondRHS, LHS) &&
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selectCCOpsAreFMaxCompatible(CondLHS, RHS)) {
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IsReversed = true ; // x CC y ? y : x
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} else {
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return SDValue();
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}
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bool IsUnordered = false, IsOrEqual;
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switch (CC) {
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default:
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return SDValue();
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case ISD::SETULT:
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case ISD::SETULE:
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IsUnordered = true;
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case ISD::SETOLT:
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case ISD::SETOLE:
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case ISD::SETLT:
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case ISD::SETLE:
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IsOrEqual = (CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE);
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Opcode = IsReversed ? AArch64ISD::FMAX : AArch64ISD::FMIN;
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break;
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case ISD::SETUGT:
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case ISD::SETUGE:
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IsUnordered = true;
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case ISD::SETOGT:
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case ISD::SETOGE:
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case ISD::SETGT:
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case ISD::SETGE:
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IsOrEqual = (CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE);
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Opcode = IsReversed ? AArch64ISD::FMIN : AArch64ISD::FMAX;
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break;
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}
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// If LHS is NaN, an ordered comparison will be false and the result will be
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// the RHS, but FMIN(NaN, RHS) = FMAX(NaN, RHS) = NaN. Avoid this by checking
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// that LHS != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
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if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
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return SDValue();
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// For xxx-or-equal comparisons, "+0 <= -0" and "-0 >= +0" will both be true,
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// but FMIN will return -0, and FMAX will return +0. So FMIN/FMAX can only be
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// used for unsafe math or if one of the operands is known to be nonzero.
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if (IsOrEqual && !DAG.getTarget().Options.UnsafeFPMath &&
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!(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
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return SDValue();
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return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), LHS, RHS);
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}
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SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
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DAGCombinerInfo &DCI) const {
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SelectionDAG &DAG = DCI.DAG;
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@ -8767,6 +8798,8 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
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return performSelectCombine(N, DCI);
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case ISD::VSELECT:
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return performVSelectCombine(N, DCI.DAG);
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case ISD::SELECT_CC:
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return performSelectCCCombine(N, DCI.DAG);
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case ISD::STORE:
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return performSTORECombine(N, DCI, DAG, Subtarget);
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case AArch64ISD::BRCOND:
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@ -3521,9 +3521,6 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
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// c = fcmp [?gt, ?ge, ?lt, ?le] a, b
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// select c, a, b
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// In NoNaNsFPMath the CC will have been changed from, e.g., 'ogt' to 'gt'.
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// FIXME: There is similar code that allows some extensions in
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// AArch64TargetLowering::LowerSELECT_CC that should be shared with this
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// code.
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bool swapSides = false;
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if (!getTargetMachine().Options.NoNaNsFPMath) {
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// transformability may depend on which way around we compare
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@ -1,29 +1,49 @@
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; RUN: llc -march=arm64 -enable-no-nans-fp-math < %s | FileCheck %s
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; RUN: llc -march=arm64 < %s | FileCheck %s --check-prefix=CHECK-SAFE
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define double @test_direct(float %in) #1 {
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define double @test_direct(float %in) {
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; CHECK-LABEL: test_direct:
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; CHECK-SAFE-LABEL: test_direct:
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%cmp = fcmp olt float %in, 0.000000e+00
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%longer = fpext float %in to double
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%val = select i1 %cmp, double 0.000000e+00, double %longer
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ret double %val
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; CHECK: fmax
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; CHECK-SAFE: fmax
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}
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define double @test_cross(float %in) #1 {
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define double @test_cross(float %in) {
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; CHECK-LABEL: test_cross:
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; CHECK-SAFE-LABEL: test_cross:
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%cmp = fcmp ult float %in, 0.000000e+00
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%longer = fpext float %in to double
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%val = select i1 %cmp, double %longer, double 0.000000e+00
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ret double %val
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; CHECK: fmin
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; CHECK-SAFE: fmin
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}
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; Same as previous, but with ordered comparison;
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; can't be converted in safe-math mode.
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define double @test_cross_fail_nan(float %in) {
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; CHECK-LABEL: test_cross_fail_nan:
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; CHECK-SAFE-LABEL: test_cross_fail_nan:
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%cmp = fcmp olt float %in, 0.000000e+00
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%longer = fpext float %in to double
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%val = select i1 %cmp, double %longer, double 0.000000e+00
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ret double %val
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; CHECK: fmin
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; CHECK-SAFE: fcsel d0, d1, d0, mi
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}
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; This isn't a min or a max, but passes the first condition for swapping the
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; results. Make sure they're put back before we resort to the normal fcsel.
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define float @test_cross_fail(float %lhs, float %rhs) {
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; CHECK-LABEL: test_cross_fail:
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; CHECK-SAFE-LABEL: test_cross_fail:
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%tst = fcmp une float %lhs, %rhs
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%res = select i1 %tst, float %rhs, float %lhs
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ret float %res
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@ -31,4 +51,12 @@ define float @test_cross_fail(float %lhs, float %rhs) {
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; The register allocator would have to decide to be deliberately obtuse before
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; other register were used.
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; CHECK: fcsel s0, s1, s0, ne
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}
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; CHECK-SAFE: fcsel s0, s1, s0, ne
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}
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; Make sure the transformation isn't triggered for integers
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define i64 @test_integer(i64 %in) {
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%cmp = icmp slt i64 %in, 0
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%val = select i1 %cmp, i64 0, i64 %in
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ret i64 %val
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}
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