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Update tests to handle MC-inst instruction printing of shift operations. The

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legacy asm printer uses instructions of the form, "mov r0, r0, lsl #3", while
the MC-instruction printer uses the form "lsl r0, r0, #3". The latter mnemonic
is correct and preferred according the ARM documentation (A8.6.98). The former
are pseudo-instructions for the latter.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114221 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2010-09-17 21:58:46 +00:00
parent f437f73348
commit 9ce75625eb
4 changed files with 7 additions and 7 deletions
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2
test/CodeGen/ARM/ispositive.ll
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@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm | FileCheck %s
define i32 @test1(i32 %X) {
; CHECK: mov r0, r0, lsr #31
; CHECK: lsr{{.*}}#31
entry:
icmp slt i32 %X, 0 ; <i1>:0 [#uses=1]
zext i1 %0 to i32 ; <i32>:1 [#uses=1]