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[AVX512] Move DAG for all-zero node to X86VectorVTInfo

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No functional change.

No change in X86.td.expanded except for the appearance of the new attributes.

The new attributes will be used in the subsequent patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219360 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Adam Nemet 2014-10-08 23:25:31 +00:00
parent 74459cbc37
commit 9d0ec9212b
1 changed files with 6 additions and 3 deletions
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9
lib/Target/X86/X86InstrAVX512.td
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@ -79,6 +79,11 @@ class X86VectorVTInfo<int NumElts, ValueType EltVT, RegisterClass rc,
Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
!if (!eq (EltTypeName, "f64"), SSEPackedDouble,
SSEPackedInt));
// A vector type of the same width with element type i32. This is used to
// create the canonical constant zero node ImmAllZerosV.
ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
}
def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
@ -171,9 +176,7 @@ multiclass AVX512_masking_common<bits<8> O, Format F, X86VectorVTInfo _,
[(set _.RC:$dst, RHS)],
[(set _.RC:$dst, MaskingRHS)],
[(set _.RC:$dst,
(vselect _.KRCWM:$mask, RHS,
(_.VT (bitconvert
(v16i32 immAllZerosV)))))],
(vselect _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
MaskingConstraint, NoItinerary, IsCommutable>;
// This multiclass generates the unconditional/non-masking, the masking and