mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Live ranges for Return value and return address of a Call are now
created here, simply by handling all implicit operands (which should have been done anyway). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3969 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vikram S. Adve
parent
f425884e27
commit
9d67cd1468
@ -78,6 +78,48 @@ void LiveRangeInfo::unionAndUpdateLRs(LiveRange *L1, LiveRange *L2) {
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}
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//---------------------------------------------------------------------------
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// Method for creating a single live range for a definition.
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// The definition must be represented by a virtual register (a Value).
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// Note: this function does *not* check that no live range exists for def.
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//---------------------------------------------------------------------------
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LiveRange*
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LiveRangeInfo::createNewLiveRange(const Value* Def, bool isCC /* = false*/)
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{
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LiveRange* DefRange = new LiveRange(); // Create a new live range,
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DefRange->insert(Def); // add Def to it,
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LiveRangeMap[Def] = DefRange; // and update the map.
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// set the register class of the new live range
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DefRange->setRegClass(RegClassList[MRI.getRegClassIDOfValue(Def, isCC)]);
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if (DEBUG_RA >= RA_DEBUG_LiveRanges) {
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cerr << " Creating a LR for def ";
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if (isCC) cerr << " (CC Register!)";
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cerr << " : " << RAV(Def) << "\n";
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}
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return DefRange;
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}
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LiveRange*
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LiveRangeInfo::createOrAddToLiveRange(const Value* Def, bool isCC /* = false*/)
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{
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LiveRange *DefRange = LiveRangeMap[Def];
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// check if the LR is already there (because of multiple defs)
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if (!DefRange) {
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DefRange = this->createNewLiveRange(Def, isCC);
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} else { // live range already exists
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DefRange->insert(Def); // add the operand to the range
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LiveRangeMap[Def] = DefRange; // make operand point to merged set
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if (DEBUG_RA >= RA_DEBUG_LiveRanges)
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cerr << " Added to existing LR for def: " << RAV(Def) << "\n";
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}
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return DefRange;
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}
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//---------------------------------------------------------------------------
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// Method for constructing all live ranges in a function. It creates live
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@ -91,128 +133,66 @@ void LiveRangeInfo::constructLiveRanges() {
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// first find the live ranges for all incoming args of the function since
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// those LRs start from the start of the function
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for (Function::const_aiterator AI = Meth->abegin(); AI != Meth->aend(); ++AI){
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LiveRange *ArgRange = new LiveRange(); // creates a new LR and
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ArgRange->insert(AI); // add the arg (def) to it
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LiveRangeMap[AI] = ArgRange;
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// create a temp machine op to find the register class of value
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//const MachineOperand Op(MachineOperand::MO_VirtualRegister);
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unsigned rcid = MRI.getRegClassIDOfValue(AI);
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ArgRange->setRegClass(RegClassList[rcid]);
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if( DEBUG_RA >= RA_DEBUG_LiveRanges)
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cerr << " Adding LiveRange for argument " << RAV(AI) << "\n";
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}
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for (Function::const_aiterator AI = Meth->abegin(); AI != Meth->aend(); ++AI)
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this->createNewLiveRange(AI, /*isCC*/ false);
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// Now suggest hardware registers for these function args
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MRI.suggestRegs4MethodArgs(Meth, *this);
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// Now find speical LLVM instructions (CALL, RET) and LRs in machine
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// instructions.
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// Now create LRs for machine instructions. A new LR will be created
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// only for defs in the machine instr since, we assume that all Values are
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// defined before they are used. However, there can be multiple defs for
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// the same Value in machine instructions.
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//
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// Also, find CALL and RETURN instructions, which need extra work.
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//
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for (Function::const_iterator BBI=Meth->begin(); BBI != Meth->end(); ++BBI){
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// Now find all LRs for machine the instructions. A new LR will be created
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// only for defs in the machine instr since, we assume that all Values are
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// defined before they are used. However, there can be multiple defs for
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// the same Value in machine instructions.
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// get the iterator for machine instructions
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// get the vector of machine instructions for this basic block.
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MachineCodeForBasicBlock& MIVec = MachineCodeForBasicBlock::get(BBI);
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// iterate over all the machine instructions in BB
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for(MachineCodeForBasicBlock::iterator MInstIterator = MIVec.begin();
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MInstIterator != MIVec.end(); ++MInstIterator) {
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MachineInstr *MInst = *MInstIterator;
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// Now if the machine instruction is a call/return instruction,
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// add it to CallRetInstrList for processing its implicit operands
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// If the machine instruction is a call/return instruction, add it to
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// CallRetInstrList for processing its args, ret value, and ret addr.
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//
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if(TM.getInstrInfo().isReturn(MInst->getOpCode()) ||
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TM.getInstrInfo().isCall(MInst->getOpCode()))
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CallRetInstrList.push_back( MInst );
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// iterate over MI operands to find defs
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// iterate over explicit MI operands and create a new LR
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// for each operand that is defined by the instruction
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for (MachineInstr::val_op_iterator OpI = MInst->begin(),
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OpE = MInst->end(); OpI != OpE; ++OpI) {
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if(DEBUG_RA >= RA_DEBUG_LiveRanges) {
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MachineOperand::MachineOperandType OpTyp =
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OpI.getMachineOperand().getOperandType();
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if (OpTyp == MachineOperand::MO_CCRegister)
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cerr << "\n**CC reg found. Is Def=" << OpI.isDef() << " Val:"
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<< RAV(OpI.getMachineOperand().getVRegValue()) << "\n";
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}
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// create a new LR iff this operand is a def
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OpE = MInst->end(); OpI != OpE; ++OpI)
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if (OpI.isDef()) {
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const Value *Def = *OpI;
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bool isCC = (OpI.getMachineOperand().getOperandType()
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== MachineOperand::MO_CCRegister);
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this->createOrAddToLiveRange(Def, isCC);
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}
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// Only instruction values are accepted for live ranges here
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if (Def->getValueType() != Value::InstructionVal ) {
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cerr << "\n**%%Error: Def is not an instruction val. Def="
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<< RAV(Def) << "\n";
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continue;
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}
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LiveRange *DefRange = LiveRangeMap[Def];
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// see LR already there (because of multiple defs)
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if( !DefRange) { // if it is not in LiveRangeMap
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DefRange = new LiveRange(); // creates a new live range and
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DefRange->insert(Def); // add the instruction (def) to it
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LiveRangeMap[ Def ] = DefRange; // update the map
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if (DEBUG_RA >= RA_DEBUG_LiveRanges)
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cerr << " creating a LR for def: " << RAV(Def) << "\n";
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// set the register class of the new live range
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//assert( RegClassList.size() );
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MachineOperand::MachineOperandType OpTy =
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OpI.getMachineOperand().getOperandType();
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bool isCC = ( OpTy == MachineOperand::MO_CCRegister);
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unsigned rcid = MRI.getRegClassIDOfValue(
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OpI.getMachineOperand().getVRegValue(), isCC );
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if (isCC && DEBUG_RA >= RA_DEBUG_LiveRanges)
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cerr << "\a**created a LR for a CC reg:"
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<< RAV(OpI.getMachineOperand().getVRegValue());
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DefRange->setRegClass(RegClassList[rcid]);
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} else {
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DefRange->insert(Def); // add the opearand to def range
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// update the map - Operand points
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// to the merged set
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LiveRangeMap[Def] = DefRange;
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if (DEBUG_RA >= RA_DEBUG_LiveRanges)
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cerr << " Added to existing LR for def: " << RAV(Def) << "\n";
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}
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} // if isDef()
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} // for all opereands in machine instructions
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// iterate over implicit MI operands and create a new LR
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// for each operand that is defined by the instruction
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for (unsigned i = 0; i < MInst->getNumImplicitRefs(); ++i)
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if (MInst->implicitRefIsDefined(i)) {
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const Value *Def = MInst->getImplicitRef(i);
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this->createOrAddToLiveRange(Def, /*isCC*/ false);
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}
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} // for all machine instructions in the BB
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} // for all BBs in function
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// Now we have to suggest clors for call and return arg live ranges.
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// Also, if there are implicit defs (e.g., retun value of a call inst)
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// they must be added to the live range list
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//
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suggestRegs4CallRets();
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if( DEBUG_RA >= RA_DEBUG_LiveRanges)
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cerr << "Initial Live Ranges constructed!\n";
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}
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@ -236,7 +216,7 @@ void LiveRangeInfo::suggestRegs4CallRets()
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MRI.suggestReg4RetValue( MInst, *this);
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else if( (TM.getInstrInfo()).isCall( OpCode ) )
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MRI.suggestRegs4CallArgs( MInst, *this, RegClassList );
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MRI.suggestRegs4CallArgs( MInst, *this);
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else
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assert( 0 && "Non call/ret instr in CallRetInstrList" );
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@ -78,6 +78,48 @@ void LiveRangeInfo::unionAndUpdateLRs(LiveRange *L1, LiveRange *L2) {
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}
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//---------------------------------------------------------------------------
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// Method for creating a single live range for a definition.
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// The definition must be represented by a virtual register (a Value).
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// Note: this function does *not* check that no live range exists for def.
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//---------------------------------------------------------------------------
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LiveRange*
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LiveRangeInfo::createNewLiveRange(const Value* Def, bool isCC /* = false*/)
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{
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LiveRange* DefRange = new LiveRange(); // Create a new live range,
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DefRange->insert(Def); // add Def to it,
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LiveRangeMap[Def] = DefRange; // and update the map.
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// set the register class of the new live range
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DefRange->setRegClass(RegClassList[MRI.getRegClassIDOfValue(Def, isCC)]);
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if (DEBUG_RA >= RA_DEBUG_LiveRanges) {
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cerr << " Creating a LR for def ";
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if (isCC) cerr << " (CC Register!)";
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cerr << " : " << RAV(Def) << "\n";
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}
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return DefRange;
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}
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LiveRange*
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LiveRangeInfo::createOrAddToLiveRange(const Value* Def, bool isCC /* = false*/)
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{
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LiveRange *DefRange = LiveRangeMap[Def];
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// check if the LR is already there (because of multiple defs)
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if (!DefRange) {
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DefRange = this->createNewLiveRange(Def, isCC);
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} else { // live range already exists
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DefRange->insert(Def); // add the operand to the range
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LiveRangeMap[Def] = DefRange; // make operand point to merged set
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if (DEBUG_RA >= RA_DEBUG_LiveRanges)
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cerr << " Added to existing LR for def: " << RAV(Def) << "\n";
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}
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return DefRange;
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}
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//---------------------------------------------------------------------------
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// Method for constructing all live ranges in a function. It creates live
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@ -91,128 +133,66 @@ void LiveRangeInfo::constructLiveRanges() {
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// first find the live ranges for all incoming args of the function since
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// those LRs start from the start of the function
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for (Function::const_aiterator AI = Meth->abegin(); AI != Meth->aend(); ++AI){
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LiveRange *ArgRange = new LiveRange(); // creates a new LR and
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ArgRange->insert(AI); // add the arg (def) to it
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LiveRangeMap[AI] = ArgRange;
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// create a temp machine op to find the register class of value
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//const MachineOperand Op(MachineOperand::MO_VirtualRegister);
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unsigned rcid = MRI.getRegClassIDOfValue(AI);
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ArgRange->setRegClass(RegClassList[rcid]);
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if( DEBUG_RA >= RA_DEBUG_LiveRanges)
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cerr << " Adding LiveRange for argument " << RAV(AI) << "\n";
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}
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for (Function::const_aiterator AI = Meth->abegin(); AI != Meth->aend(); ++AI)
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this->createNewLiveRange(AI, /*isCC*/ false);
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// Now suggest hardware registers for these function args
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MRI.suggestRegs4MethodArgs(Meth, *this);
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// Now find speical LLVM instructions (CALL, RET) and LRs in machine
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// instructions.
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// Now create LRs for machine instructions. A new LR will be created
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// only for defs in the machine instr since, we assume that all Values are
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// defined before they are used. However, there can be multiple defs for
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// the same Value in machine instructions.
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//
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// Also, find CALL and RETURN instructions, which need extra work.
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//
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for (Function::const_iterator BBI=Meth->begin(); BBI != Meth->end(); ++BBI){
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// Now find all LRs for machine the instructions. A new LR will be created
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// only for defs in the machine instr since, we assume that all Values are
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// defined before they are used. However, there can be multiple defs for
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// the same Value in machine instructions.
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// get the iterator for machine instructions
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// get the vector of machine instructions for this basic block.
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MachineCodeForBasicBlock& MIVec = MachineCodeForBasicBlock::get(BBI);
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// iterate over all the machine instructions in BB
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for(MachineCodeForBasicBlock::iterator MInstIterator = MIVec.begin();
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MInstIterator != MIVec.end(); ++MInstIterator) {
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MachineInstr *MInst = *MInstIterator;
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// Now if the machine instruction is a call/return instruction,
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// add it to CallRetInstrList for processing its implicit operands
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// If the machine instruction is a call/return instruction, add it to
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// CallRetInstrList for processing its args, ret value, and ret addr.
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//
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if(TM.getInstrInfo().isReturn(MInst->getOpCode()) ||
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TM.getInstrInfo().isCall(MInst->getOpCode()))
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CallRetInstrList.push_back( MInst );
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// iterate over MI operands to find defs
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// iterate over explicit MI operands and create a new LR
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// for each operand that is defined by the instruction
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for (MachineInstr::val_op_iterator OpI = MInst->begin(),
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OpE = MInst->end(); OpI != OpE; ++OpI) {
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if(DEBUG_RA >= RA_DEBUG_LiveRanges) {
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MachineOperand::MachineOperandType OpTyp =
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OpI.getMachineOperand().getOperandType();
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if (OpTyp == MachineOperand::MO_CCRegister)
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cerr << "\n**CC reg found. Is Def=" << OpI.isDef() << " Val:"
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<< RAV(OpI.getMachineOperand().getVRegValue()) << "\n";
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}
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// create a new LR iff this operand is a def
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OpE = MInst->end(); OpI != OpE; ++OpI)
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if (OpI.isDef()) {
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const Value *Def = *OpI;
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bool isCC = (OpI.getMachineOperand().getOperandType()
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== MachineOperand::MO_CCRegister);
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this->createOrAddToLiveRange(Def, isCC);
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}
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// Only instruction values are accepted for live ranges here
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if (Def->getValueType() != Value::InstructionVal ) {
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cerr << "\n**%%Error: Def is not an instruction val. Def="
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<< RAV(Def) << "\n";
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continue;
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}
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LiveRange *DefRange = LiveRangeMap[Def];
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// see LR already there (because of multiple defs)
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if( !DefRange) { // if it is not in LiveRangeMap
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DefRange = new LiveRange(); // creates a new live range and
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DefRange->insert(Def); // add the instruction (def) to it
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LiveRangeMap[ Def ] = DefRange; // update the map
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if (DEBUG_RA >= RA_DEBUG_LiveRanges)
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cerr << " creating a LR for def: " << RAV(Def) << "\n";
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// set the register class of the new live range
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//assert( RegClassList.size() );
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MachineOperand::MachineOperandType OpTy =
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OpI.getMachineOperand().getOperandType();
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bool isCC = ( OpTy == MachineOperand::MO_CCRegister);
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unsigned rcid = MRI.getRegClassIDOfValue(
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OpI.getMachineOperand().getVRegValue(), isCC );
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if (isCC && DEBUG_RA >= RA_DEBUG_LiveRanges)
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cerr << "\a**created a LR for a CC reg:"
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<< RAV(OpI.getMachineOperand().getVRegValue());
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DefRange->setRegClass(RegClassList[rcid]);
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} else {
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DefRange->insert(Def); // add the opearand to def range
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// update the map - Operand points
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// to the merged set
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LiveRangeMap[Def] = DefRange;
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if (DEBUG_RA >= RA_DEBUG_LiveRanges)
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cerr << " Added to existing LR for def: " << RAV(Def) << "\n";
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}
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} // if isDef()
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} // for all opereands in machine instructions
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// iterate over implicit MI operands and create a new LR
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// for each operand that is defined by the instruction
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for (unsigned i = 0; i < MInst->getNumImplicitRefs(); ++i)
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if (MInst->implicitRefIsDefined(i)) {
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const Value *Def = MInst->getImplicitRef(i);
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this->createOrAddToLiveRange(Def, /*isCC*/ false);
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}
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} // for all machine instructions in the BB
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} // for all BBs in function
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// Now we have to suggest clors for call and return arg live ranges.
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// Also, if there are implicit defs (e.g., retun value of a call inst)
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// they must be added to the live range list
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//
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suggestRegs4CallRets();
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if( DEBUG_RA >= RA_DEBUG_LiveRanges)
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cerr << "Initial Live Ranges constructed!\n";
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}
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@ -236,7 +216,7 @@ void LiveRangeInfo::suggestRegs4CallRets()
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MRI.suggestReg4RetValue( MInst, *this);
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else if( (TM.getInstrInfo()).isCall( OpCode ) )
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MRI.suggestRegs4CallArgs( MInst, *this, RegClassList );
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MRI.suggestRegs4CallArgs( MInst, *this);
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else
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assert( 0 && "Non call/ret instr in CallRetInstrList" );
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