From 9d6c45bdd71cfa6d0aace1a3d2da82d7351010eb Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Wed, 17 Aug 2005 17:08:24 +0000 Subject: [PATCH] Fix some bugs in the alpha backend, some of which I introduced yesterday, and some that were preexisting. All alpha regtests pass now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22829 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Alpha/AlphaISelPattern.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp index 80a47a1a9d0..e559852d2b9 100644 --- a/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/lib/Target/Alpha/AlphaISelPattern.cpp @@ -284,6 +284,7 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) case MVT::f32: args_float[count] = AddLiveIn(MF,args_float[count], getRegClassFor(VT)); argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[count], VT); + DAG.setRoot(argt.getValue(1)); break; case MVT::i1: case MVT::i8: @@ -292,12 +293,12 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) case MVT::i64: args_int[count] = AddLiveIn(MF, args_int[count], getRegClassFor(MVT::i64)); - argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[count], VT); + argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[count], MVT::i64); + DAG.setRoot(argt.getValue(1)); if (VT != MVT::i64) argt = DAG.getNode(ISD::TRUNCATE, VT, argt); break; } - DAG.setRoot(argt.getValue(1)); } else { //more args // Create the frame index object for this incoming parameter... int FI = MFI->CreateFixedObject(8, 8 * (count - 6));