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Enable machine cse of instructions which define physical registers.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105308 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2010-06-02 01:08:27 +00:00
parent 22237771d8
commit 9d709a8edb
2 changed files with 19 additions and 4 deletions
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5
lib/CodeGen/MachineCSE.cpp
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@ -31,9 +31,6 @@ using namespace llvm;
STATISTIC(NumCoalesces, "Number of copies coalesced");
STATISTIC(NumCSEs, "Number of common subexpression eliminated");
static cl::opt<bool> CSEPhysDef("machine-cse-phys-defs",
cl::init(false), cl::Hidden);
namespace {
class MachineCSE : public MachineFunctionPass {
const TargetInstrInfo *TII;
@ -376,7 +373,7 @@ bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) {
// ... Unless the CS is local and it also defines the physical register
// which is not clobbered in between.
if (PhysDef && CSEPhysDef) {
if (PhysDef) {
unsigned CSVN = VNT.lookup(MI);
MachineInstr *CSMI = Exps[CSVN];
if (PhysRegDefReaches(CSMI, MI, PhysDef))

18
test/CodeGen/ARM/machine-cse-cmp.ll Normal file
View File

@ -0,0 +1,18 @@
; RUN: llc < %s -march=arm | FileCheck %s
;rdar://8003725
@G1 = external global i32
@G2 = external global i32
define i32 @f1(i32 %cond1, i32 %x1, i32 %x2, i32 %x3) {
entry:
; CHECK: cmp
; CHECK: moveq
; CHECK-NOT: cmp
; CHECK: moveq
%tmp1 = icmp eq i32 %cond1, 0
%tmp2 = select i1 %tmp1, i32 %x1, i32 %x2
%tmp3 = select i1 %tmp1, i32 %x2, i32 %x3
%tmp4 = add i32 %tmp2, %tmp3
ret i32 %tmp4
}