From 9dc4d3cbac284b8301832fb1b575364490c745f3 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Mon, 22 Aug 2005 22:00:02 +0000 Subject: [PATCH] Nate noticed that 30% of the malloc/frees in llc come from calls to LowercaseString in the asmprinter. This changes the .td files to use lower case register names, avoiding the need to do this call. This speeds up the asmprinter from 1.52s to 1.06s on kc++ in a release build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22974 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCAsmPrinter.cpp | 4 +- lib/Target/PowerPC/PPCRegisterInfo.td | 84 +++++++++++++-------------- 2 files changed, 44 insertions(+), 44 deletions(-) diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp index 840d7383fce..10a6dbce728 100644 --- a/lib/Target/PowerPC/PPCAsmPrinter.cpp +++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -89,7 +89,7 @@ namespace { const MachineOperand &MO = MI->getOperand(OpNo); if (MO.getType() == MachineOperand::MO_MachineRegister) { assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??"); - O << LowercaseString(TM.getRegisterInfo()->get(MO.getReg()).Name); + O << TM.getRegisterInfo()->get(MO.getReg()).Name; } else if (MO.isImmediate()) { O << MO.getImmedValue(); } else { @@ -275,7 +275,7 @@ void PowerPCAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) { // FALLTHROUGH case MachineOperand::MO_MachineRegister: case MachineOperand::MO_CCRegister: - O << LowercaseString(RI.get(MO.getReg()).Name); + O << RI.get(MO.getReg()).Name; return; case MachineOperand::MO_SignExtendedImmed: diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td index b741a2a843b..04db90c041e 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/lib/Target/PowerPC/PPCRegisterInfo.td @@ -37,57 +37,57 @@ class CR num, string n> : PPCReg { } // General-purpose registers -def R0 : GPR< 0, "R0">; def R1 : GPR< 1, "R1">; -def R2 : GPR< 2, "R2">; def R3 : GPR< 3, "R3">; -def R4 : GPR< 4, "R4">; def R5 : GPR< 5, "R5">; -def R6 : GPR< 6, "R6">; def R7 : GPR< 7, "R7">; -def R8 : GPR< 8, "R8">; def R9 : GPR< 9, "R9">; -def R10 : GPR<10, "R10">; def R11 : GPR<11, "R11">; -def R12 : GPR<12, "R12">; def R13 : GPR<13, "R13">; -def R14 : GPR<14, "R14">; def R15 : GPR<15, "R15">; -def R16 : GPR<16, "R16">; def R17 : GPR<17, "R17">; -def R18 : GPR<18, "R18">; def R19 : GPR<19, "R19">; -def R20 : GPR<20, "R20">; def R21 : GPR<21, "R21">; -def R22 : GPR<22, "R22">; def R23 : GPR<23, "R23">; -def R24 : GPR<24, "R24">; def R25 : GPR<25, "R25">; -def R26 : GPR<26, "R26">; def R27 : GPR<27, "R27">; -def R28 : GPR<28, "R28">; def R29 : GPR<29, "R29">; -def R30 : GPR<30, "R30">; def R31 : GPR<31, "R31">; +def R0 : GPR< 0, "r0">; def R1 : GPR< 1, "r1">; +def R2 : GPR< 2, "r2">; def R3 : GPR< 3, "r3">; +def R4 : GPR< 4, "r4">; def R5 : GPR< 5, "r5">; +def R6 : GPR< 6, "r6">; def R7 : GPR< 7, "r7">; +def R8 : GPR< 8, "r8">; def R9 : GPR< 9, "r9">; +def R10 : GPR<10, "r10">; def R11 : GPR<11, "r11">; +def R12 : GPR<12, "r12">; def R13 : GPR<13, "r13">; +def R14 : GPR<14, "r14">; def R15 : GPR<15, "r15">; +def R16 : GPR<16, "r16">; def R17 : GPR<17, "r17">; +def R18 : GPR<18, "r18">; def R19 : GPR<19, "r19">; +def R20 : GPR<20, "r20">; def R21 : GPR<21, "r21">; +def R22 : GPR<22, "r22">; def R23 : GPR<23, "r23">; +def R24 : GPR<24, "r24">; def R25 : GPR<25, "r25">; +def R26 : GPR<26, "r26">; def R27 : GPR<27, "r27">; +def R28 : GPR<28, "r28">; def R29 : GPR<29, "r29">; +def R30 : GPR<30, "r30">; def R31 : GPR<31, "r31">; // Floating-point registers -def F0 : FPR< 0, "F0">; def F1 : FPR< 1, "F1">; -def F2 : FPR< 2, "F2">; def F3 : FPR< 3, "F3">; -def F4 : FPR< 4, "F4">; def F5 : FPR< 5, "F5">; -def F6 : FPR< 6, "F6">; def F7 : FPR< 7, "F7">; -def F8 : FPR< 8, "F8">; def F9 : FPR< 9, "F9">; -def F10 : FPR<10, "F10">; def F11 : FPR<11, "F11">; -def F12 : FPR<12, "F12">; def F13 : FPR<13, "F13">; -def F14 : FPR<14, "F14">; def F15 : FPR<15, "F15">; -def F16 : FPR<16, "F16">; def F17 : FPR<17, "F17">; -def F18 : FPR<18, "F18">; def F19 : FPR<19, "F19">; -def F20 : FPR<20, "F20">; def F21 : FPR<21, "F21">; -def F22 : FPR<22, "F22">; def F23 : FPR<23, "F23">; -def F24 : FPR<24, "F24">; def F25 : FPR<25, "F25">; -def F26 : FPR<26, "F26">; def F27 : FPR<27, "F27">; -def F28 : FPR<28, "F28">; def F29 : FPR<29, "F29">; -def F30 : FPR<30, "F30">; def F31 : FPR<31, "F31">; +def F0 : FPR< 0, "f0">; def F1 : FPR< 1, "f1">; +def F2 : FPR< 2, "f2">; def F3 : FPR< 3, "f3">; +def F4 : FPR< 4, "f4">; def F5 : FPR< 5, "f5">; +def F6 : FPR< 6, "f6">; def F7 : FPR< 7, "f7">; +def F8 : FPR< 8, "f8">; def F9 : FPR< 9, "f9">; +def F10 : FPR<10, "f10">; def F11 : FPR<11, "f11">; +def F12 : FPR<12, "f12">; def F13 : FPR<13, "f13">; +def F14 : FPR<14, "f14">; def F15 : FPR<15, "f15">; +def F16 : FPR<16, "f16">; def F17 : FPR<17, "f17">; +def F18 : FPR<18, "f18">; def F19 : FPR<19, "f19">; +def F20 : FPR<20, "f20">; def F21 : FPR<21, "f21">; +def F22 : FPR<22, "f22">; def F23 : FPR<23, "f23">; +def F24 : FPR<24, "f24">; def F25 : FPR<25, "f25">; +def F26 : FPR<26, "f26">; def F27 : FPR<27, "f27">; +def F28 : FPR<28, "f28">; def F29 : FPR<29, "f29">; +def F30 : FPR<30, "f30">; def F31 : FPR<31, "f31">; // Condition registers -def CR0 : CR<0, "CR0">; def CR1 : CR<1, "CR1">; -def CR2 : CR<2, "CR2">; def CR3 : CR<3, "CR3">; -def CR4 : CR<4, "CR4">; def CR5 : CR<5, "CR5">; -def CR6 : CR<6, "CR6">; def CR7 : CR<7, "CR7">; +def CR0 : CR<0, "cr0">; def CR1 : CR<1, "cr1">; +def CR2 : CR<2, "cr2">; def CR3 : CR<3, "cr3">; +def CR4 : CR<4, "cr4">; def CR5 : CR<5, "cr5">; +def CR6 : CR<6, "cr6">; def CR7 : CR<7, "cr7">; // Floating-point status and control register -def FPSCR : SPR<0, "FPSCR">; +def FPSCR : SPR<0, "fpscr">; // fiXed-point Exception Register? :-) -def XER : SPR<1, "XER">; +def XER : SPR<1, "xer">; // Link register -def LR : SPR<2, "LR">; +def LR : SPR<2, "lr">; // Count register -def CTR : SPR<3, "CTR">; +def CTR : SPR<3, "ctr">; // These are the "time base" registers which are read-only in user mode. -def TBL : SPR<4, "TBL">; -def TBU : SPR<5, "TBU">; +def TBL : SPR<4, "tbl">; +def TBU : SPR<5, "tbu">;