mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-08-07 12:28:24 +00:00
Fix trailing whitespace and style, no functionality change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118515 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes
@@ -126,88 +126,58 @@ def addr : ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], []>;
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let isCommutable = 1 in
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class ArithR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
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InstrItinClass itin>:
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FR< op,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], itin>;
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let isCommutable = 1 in
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class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm>:
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FR< op,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[], IIAlu>;
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FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"), [], IIAlu>;
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// Arithmetic 2 register operands
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class ArithI<bits<6> op, string instr_asm, SDNode OpNode,
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Operand Od, PatLeaf imm_type> :
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FI< op,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, Od:$c),
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FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, Od:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, imm_type:$c))], IIAlu>;
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class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode,
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Operand Od, PatLeaf imm_type> :
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FI< op,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, Od:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[], IIAlu>;
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FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, Od:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"), [], IIAlu>;
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// Arithmetic Multiply ADD/SUB
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let rd=0 in
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class MArithR<bits<6> func, string instr_asm> :
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FR< 0x1c,
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func,
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(outs CPURegs:$rs),
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(ins CPURegs:$rt),
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!strconcat(instr_asm, "\t$rs, $rt"),
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[], IIImul>;
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FR<0x1c, func, (outs CPURegs:$rs), (ins CPURegs:$rt),
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!strconcat(instr_asm, "\t$rs, $rt"), [], IIImul>;
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// Logical
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class LogicR<bits<6> func, string instr_asm, SDNode OpNode>:
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FR< 0x00,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
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class LogicI<bits<6> op, string instr_asm, SDNode OpNode>:
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FI< op,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, uimm16:$c),
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FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, uimm16:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt16:$c))], IIAlu>;
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class LogicNOR<bits<6> op, bits<6> func, string instr_asm>:
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FR< op,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (not (or CPURegs:$b, CPURegs:$c)))], IIAlu>;
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// Shifts
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let rt = 0 in
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class LogicR_shift_imm<bits<6> func, string instr_asm, SDNode OpNode>:
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FR< 0x00,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, shamt:$c),
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FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$b, shamt:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt5:$c))], IIAlu>;
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class LogicR_shift_reg<bits<6> func, string instr_asm, SDNode OpNode>:
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FR< 0x00,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
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@@ -222,34 +192,25 @@ class LoadUpper<bits<6> op, string instr_asm>:
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// Memory Load/Store
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let canFoldAsLoad = 1, hasDelaySlot = 1 in
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class LoadM<bits<6> op, string instr_asm, PatFrag OpNode>:
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FI< op,
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(outs CPURegs:$dst),
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(ins mem:$addr),
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FI<op, (outs CPURegs:$dst), (ins mem:$addr),
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!strconcat(instr_asm, "\t$dst, $addr"),
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[(set CPURegs:$dst, (OpNode addr:$addr))], IILoad>;
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class StoreM<bits<6> op, string instr_asm, PatFrag OpNode>:
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FI< op,
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(outs),
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(ins CPURegs:$dst, mem:$addr),
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FI<op, (outs), (ins CPURegs:$dst, mem:$addr),
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!strconcat(instr_asm, "\t$dst, $addr"),
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[(OpNode CPURegs:$dst, addr:$addr)], IIStore>;
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// Conditional Branch
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let isBranch = 1, isTerminator=1, hasDelaySlot = 1 in {
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class CBranch<bits<6> op, string instr_asm, PatFrag cond_op>:
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FI< op,
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(outs),
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(ins CPURegs:$a, CPURegs:$b, brtarget:$offset),
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FI<op, (outs), (ins CPURegs:$a, CPURegs:$b, brtarget:$offset),
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!strconcat(instr_asm, "\t$a, $b, $offset"),
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[(brcond (cond_op CPURegs:$a, CPURegs:$b), bb:$offset)],
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IIBranch>;
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class CBranchZero<bits<6> op, string instr_asm, PatFrag cond_op>:
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FI< op,
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(outs),
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(ins CPURegs:$src, brtarget:$offset),
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FI<op, (outs), (ins CPURegs:$src, brtarget:$offset),
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!strconcat(instr_asm, "\t$src, $offset"),
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[(brcond (cond_op CPURegs:$src, 0), bb:$offset)],
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IIBranch>;
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@@ -258,19 +219,14 @@ class CBranchZero<bits<6> op, string instr_asm, PatFrag cond_op>:
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// SetCC
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class SetCC_R<bits<6> op, bits<6> func, string instr_asm,
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PatFrag cond_op>:
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FR< op,
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func,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, CPURegs:$c),
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FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (cond_op CPURegs:$b, CPURegs:$c))],
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IIAlu>;
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class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op,
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Operand Od, PatLeaf imm_type>:
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FI< op,
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(outs CPURegs:$dst),
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(ins CPURegs:$b, Od:$c),
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FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, Od:$c),
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!strconcat(instr_asm, "\t$dst, $b, $c"),
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[(set CPURegs:$dst, (cond_op CPURegs:$b, imm_type:$c))],
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IIAlu>;
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@@ -278,20 +234,13 @@ class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op,
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// Unconditional branch
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let isBranch=1, isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
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class JumpFJ<bits<6> op, string instr_asm>:
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FJ< op,
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(outs),
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(ins brtarget:$target),
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!strconcat(instr_asm, "\t$target"),
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[(br bb:$target)], IIBranch>;
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FJ<op, (outs), (ins brtarget:$target),
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!strconcat(instr_asm, "\t$target"), [(br bb:$target)], IIBranch>;
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let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1 in
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class JumpFR<bits<6> op, bits<6> func, string instr_asm>:
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FR< op,
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func,
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(outs),
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(ins CPURegs:$target),
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!strconcat(instr_asm, "\t$target"),
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[(brind CPURegs:$target)], IIBranch>;
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FR<op, func, (outs), (ins CPURegs:$target),
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!strconcat(instr_asm, "\t$target"), [(brind CPURegs:$target)], IIBranch>;
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// Jump and Link (Call)
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let isCall=1, hasDelaySlot=1,
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@@ -299,83 +248,59 @@ let isCall=1, hasDelaySlot=1,
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Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
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K0, K1, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9], Uses = [GP] in {
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class JumpLink<bits<6> op, string instr_asm>:
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FJ< op,
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(outs),
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(ins calltarget:$target, variable_ops),
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!strconcat(instr_asm, "\t$target"),
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[(MipsJmpLink imm:$target)], IIBranch>;
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FJ<op, (outs), (ins calltarget:$target, variable_ops),
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!strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)],
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IIBranch>;
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let rd=31 in
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class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm>:
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FR< op,
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func,
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(outs),
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(ins CPURegs:$rs, variable_ops),
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!strconcat(instr_asm, "\t$rs"),
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[(MipsJmpLink CPURegs:$rs)], IIBranch>;
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FR<op, func, (outs), (ins CPURegs:$rs, variable_ops),
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!strconcat(instr_asm, "\t$rs"), [(MipsJmpLink CPURegs:$rs)], IIBranch>;
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class BranchLink<string instr_asm>:
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FI< 0x1,
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(outs),
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(ins CPURegs:$rs, brtarget:$target, variable_ops),
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!strconcat(instr_asm, "\t$rs, $target"),
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[], IIBranch>;
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FI<0x1, (outs), (ins CPURegs:$rs, brtarget:$target, variable_ops),
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!strconcat(instr_asm, "\t$rs, $target"), [], IIBranch>;
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}
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// Mul, Div
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class MulDiv<bits<6> func, string instr_asm, InstrItinClass itin>:
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FR< 0x00,
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func,
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(outs),
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(ins CPURegs:$a, CPURegs:$b),
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!strconcat(instr_asm, "\t$a, $b"),
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[], itin>;
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FR<0x00, func, (outs), (ins CPURegs:$a, CPURegs:$b),
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!strconcat(instr_asm, "\t$a, $b"), [], itin>;
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// Move from Hi/Lo
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class MoveFromLOHI<bits<6> func, string instr_asm>:
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FR< 0x00,
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func,
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(outs CPURegs:$dst),
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(ins),
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!strconcat(instr_asm, "\t$dst"),
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[], IIHiLo>;
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FR<0x00, func, (outs CPURegs:$dst), (ins),
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!strconcat(instr_asm, "\t$dst"), [], IIHiLo>;
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class MoveToLOHI<bits<6> func, string instr_asm>:
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FR< 0x00,
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func,
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(outs),
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(ins CPURegs:$src),
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!strconcat(instr_asm, "\t$src"),
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[], IIHiLo>;
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FR<0x00, func, (outs), (ins CPURegs:$src),
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!strconcat(instr_asm, "\t$src"), [], IIHiLo>;
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class EffectiveAddress<string instr_asm> :
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FI<0x09,
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(outs CPURegs:$dst),
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(ins mem:$addr),
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instr_asm,
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[(set CPURegs:$dst, addr:$addr)], IIAlu>;
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FI<0x09, (outs CPURegs:$dst), (ins mem:$addr),
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instr_asm, [(set CPURegs:$dst, addr:$addr)], IIAlu>;
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// Count Leading Ones/Zeros in Word
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class CountLeading<bits<6> func, string instr_asm, SDNode CountOp>:
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FR< 0x1c, func, (outs CPURegs:$dst), (ins CPURegs:$src),
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FR<0x1c, func, (outs CPURegs:$dst), (ins CPURegs:$src),
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!strconcat(instr_asm, "\t$dst, $src"),
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[(set CPURegs:$dst, (CountOp CPURegs:$src))], IIAlu>;
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// Sign Extend in Register.
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class SignExtInReg<bits<6> func, string instr_asm, ValueType vt>:
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FR< 0x3f, func, (outs CPURegs:$dst), (ins CPURegs:$src),
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FR<0x3f, func, (outs CPURegs:$dst), (ins CPURegs:$src),
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!strconcat(instr_asm, "\t$dst, $src"),
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[(set CPURegs:$dst, (sext_inreg CPURegs:$src, vt))], NoItinerary>;
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// Byte Swap
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class ByteSwap<bits<6> func, string instr_asm>:
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FR< 0x1f, func, (outs CPURegs:$dst), (ins CPURegs:$src),
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FR<0x1f, func, (outs CPURegs:$dst), (ins CPURegs:$src),
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!strconcat(instr_asm, "\t$dst, $src"),
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[(set CPURegs:$dst, (bswap CPURegs:$src))], NoItinerary>;
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// Conditional Move
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class CondMov<bits<6> func, string instr_asm, PatLeaf MovCode>:
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FR< 0x00, func, (outs CPURegs:$dst), (ins CPURegs:$F, CPURegs:$T,
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FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$F, CPURegs:$T,
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CPURegs:$cond), !strconcat(instr_asm, "\t$dst, $T, $cond"),
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[(set CPURegs:$dst, (MipsCMov CPURegs:$F, CPURegs:$T,
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CPURegs:$cond, MovCode))], NoItinerary>;
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