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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-26 07:29:55 +00:00
More ARM load/store indexed refactoring. Also fix an incorrect IndexMode
flag for the LDRT/STRT family instructions as a side effect. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118955 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -420,7 +420,7 @@ class AI1x2<dag oops, dag iops, Format f, InstrItinClass itin,
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// loads
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// LDR/LDRB/STR/STRB
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class AIldst1<bits<3> op, bit opc22, bit isLd, dag oops, dag iops, AddrMode am,
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class AIldst1<bits<3> op, bit isLd, bit isByte, dag oops, dag iops, AddrMode am,
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Format f, InstrItinClass itin, string opc, string asm,
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list<dag> pattern>
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: I<oops, iops, am, Size4Bytes, IndexModeNone, f, itin, opc, asm,
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@ -428,24 +428,21 @@ class AIldst1<bits<3> op, bit opc22, bit isLd, dag oops, dag iops, AddrMode am,
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let Inst{27-25} = op;
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let Inst{24} = 1; // 24 == P
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// 23 == U
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let Inst{22} = opc22;
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let Inst{22} = isByte;
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let Inst{21} = 0; // 21 == W
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let Inst{20} = isLd;
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}
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// LDRH/LDRSB/LDRSH/LDRD
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class AIldr2<bits<4> op, bit opc22, bit opc20, dag oops, dag iops, AddrMode am,
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Format f, InstrItinClass itin, string opc, string asm,
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list<dag> pattern>
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: I<oops, iops, am, Size4Bytes, IndexModeNone, f, itin, opc, asm,
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"", pattern> {
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let Inst{27-25} = 0b000;
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let Inst{24} = 1; // 24 == P
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// 23 == U
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let Inst{22} = opc22;
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let Inst{21} = 0; // 21 == W
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let Inst{20} = opc20;
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let Inst{7-4} = op;
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// Indexed load/stores
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class AI2ldstidx<bit isLd, bit isByte, bit isPre, dag oops, dag iops,
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IndexMode im, Format f, InstrItinClass itin, string opc,
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string asm, string cstr, list<dag> pattern>
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: I<oops, iops, AddrMode2, Size4Bytes, im, f, itin,
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opc, asm, cstr, pattern> {
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let Inst{27-26} = 0b01;
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let Inst{24} = isPre; // P bit
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let Inst{22} = isByte; // B bit
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let Inst{21} = isPre; // W bit
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let Inst{20} = isLd; // L bit
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}
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class AXI2ldw<dag oops, dag iops, Format f, InstrItinClass itin,
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@ -491,32 +488,6 @@ class AXI2stb<dag oops, dag iops, Format f, InstrItinClass itin,
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let Inst{27-26} = 0b01;
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}
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// Pre-indexed load/stores
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class AI2ldstpr<bit isLd, bit opc22, dag oops, dag iops, Format f,
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InstrItinClass itin, string opc, string asm, string cstr,
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list<dag> pattern>
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: I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, itin,
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opc, asm, cstr, pattern> {
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let Inst{20} = isLd; // L bit
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let Inst{21} = 1; // W bit
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let Inst{22} = opc22; // B bit
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let Inst{24} = 1; // P bit
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let Inst{27-26} = 0b01;
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}
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// Post-indexed load/stores
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class AI2ldstpo<bit isLd, bit opc22, dag oops, dag iops, Format f,
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InstrItinClass itin, string opc, string asm, string cstr,
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list<dag> pattern>
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: I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, itin,
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opc, asm, cstr,pattern> {
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let Inst{20} = isLd; // L bit
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let Inst{21} = 0; // W bit
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let Inst{22} = opc22; // B bit
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let Inst{24} = 0; // P bit
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let Inst{27-26} = 0b01;
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}
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// addrmode3 instructions
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class AI3<dag oops, dag iops, Format f, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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@ -845,12 +845,12 @@ multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
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}
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let canFoldAsLoad = 1, isReMaterializable = 1 in {
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multiclass AI_ldr1<bit opc22, string opc, InstrItinClass iii,
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multiclass AI_ldr1<bit isByte, string opc, InstrItinClass iii,
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InstrItinClass iir, PatFrag opnode> {
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// Note: We use the complex addrmode_imm12 rather than just an input
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// GPR and a constrained immediate so that we can use this to match
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// frame index references and avoid matching constant pool references.
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def i12 : AIldst1<0b010, opc22, 1, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
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def i12: AIldst1<0b010, 1, isByte, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
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AddrMode_i12, LdFrm, iii, opc, "\t$Rt, $addr",
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[(set GPR:$Rt, (opnode addrmode_imm12:$addr))]> {
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bits<4> Rt;
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@ -860,7 +860,7 @@ multiclass AI_ldr1<bit opc22, string opc, InstrItinClass iii,
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let Inst{15-12} = Rt;
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let Inst{11-0} = addr{11-0}; // imm12
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}
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def rs : AIldst1<0b011, opc22, 1, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
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def rs : AIldst1<0b011, 1, isByte, (outs GPR:$Rt), (ins ldst_so_reg:$shift),
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AddrModeNone, LdFrm, iir, opc, "\t$Rt, $shift",
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[(set GPR:$Rt, (opnode ldst_so_reg:$shift))]> {
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bits<4> Rt;
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@ -873,12 +873,12 @@ multiclass AI_ldr1<bit opc22, string opc, InstrItinClass iii,
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}
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}
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multiclass AI_str1<bit opc22, string opc, InstrItinClass iii,
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multiclass AI_str1<bit isByte, string opc, InstrItinClass iii,
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InstrItinClass iir, PatFrag opnode> {
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// Note: We use the complex addrmode_imm12 rather than just an input
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// GPR and a constrained immediate so that we can use this to match
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// frame index references and avoid matching constant pool references.
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def i12 : AIldst1<0b010, opc22, 0, (outs),
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def i12 : AIldst1<0b010, 0, isByte, (outs),
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(ins GPR:$Rt, addrmode_imm12:$addr),
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AddrMode_i12, StFrm, iii, opc, "\t$Rt, $addr",
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[(opnode GPR:$Rt, addrmode_imm12:$addr)]> {
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@ -889,7 +889,7 @@ multiclass AI_str1<bit opc22, string opc, InstrItinClass iii,
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let Inst{15-12} = Rt;
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let Inst{11-0} = addr{11-0}; // imm12
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}
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def rs : AIldst1<0b011, opc22, 0, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
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def rs : AIldst1<0b011, 0, isByte, (outs), (ins GPR:$Rt, ldst_so_reg:$shift),
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AddrModeNone, StFrm, iir, opc, "\t$Rt, $shift",
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[(opnode GPR:$Rt, ldst_so_reg:$shift)]> {
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bits<4> Rt;
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@ -1513,8 +1513,9 @@ defm STRB : AI_str1<1, "strb", IIC_iStore_bh_r, IIC_iStore_bh_si,
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// Special LDR for loads from non-pc-relative constpools.
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let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
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isReMaterializable = 1 in
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def LDRcp : AIldst1<0b010, 0, 1, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
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AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr", []> {
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def LDRcp : AIldst1<0b010, 1, 0, (outs GPR:$Rt), (ins addrmode_imm12:$addr),
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AddrMode_i12, LdFrm, IIC_iLoad_r, "ldr", "\t$Rt, $addr",
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[]> {
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bits<4> Rt;
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bits<17> addr;
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let Inst{23} = addr{12}; // U (add = ('U' == 1))
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@ -1545,12 +1546,15 @@ def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
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[]>, Requires<[IsARM, HasV5TE]>;
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// Indexed loads
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def LDR_PRE : AI2ldstpr<1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
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(ins addrmode2:$addr), LdFrm, IIC_iLoad_ru,
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"ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
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def LDR_PRE : AI2ldstidx<1, 0, 1, (outs GPR:$Rt, GPR:$Rn_wb),
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(ins addrmode2:$addr), IndexModePre, LdFrm, IIC_iLoad_ru,
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"ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []> {
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let Inst{21} = 1; // W bit (overwrite)
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}
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def LDR_POST : AI2ldstpo<1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
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(ins GPR:$Rn, am2offset:$offset), LdFrm, IIC_iLoad_ru,
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def LDR_POST : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
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(ins GPR:$Rn, am2offset:$offset), IndexModePost,
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LdFrm, IIC_iLoad_ru,
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"ldr", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>;
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def LDRH_PRE : AI3ldhpr<(outs GPR:$Rt, GPR:$Rn_wb),
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@ -1561,12 +1565,14 @@ def LDRH_POST : AI3ldhpo<(outs GPR:$Rt, GPR:$Rn_wb),
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(ins GPR:$Rn,am3offset:$offset), LdMiscFrm, IIC_iLoad_bh_ru,
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"ldrh", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>;
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def LDRB_PRE : AI2ldstpr<1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
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(ins addrmode2:$addr), LdFrm, IIC_iLoad_bh_ru,
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def LDRB_PRE : AI2ldstidx<1, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
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(ins addrmode2:$addr), IndexModePre, LdFrm,
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IIC_iLoad_bh_ru,
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"ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
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def LDRB_POST : AI2ldstpo<1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
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(ins GPR:$Rn,am2offset:$offset), LdFrm, IIC_iLoad_bh_ru,
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def LDRB_POST : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
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(ins GPR:$Rn,am2offset:$offset), IndexModePost,
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LdFrm, IIC_iLoad_bh_ru,
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"ldrb", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb", []>;
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def LDRSH_PRE : AI3ldshpr<(outs GPR:$Rt, GPR:$Rn_wb),
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@ -1601,14 +1607,16 @@ def LDRD_POST : AI3lddpo<(outs GPR:$dst1, GPR:$dst2, GPR:$base_wb),
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// LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
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def LDRT : AI2ldstpo<1, 0, (outs GPR:$dst, GPR:$base_wb),
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(ins GPR:$base, am2offset:$offset), LdFrm, IIC_iLoad_ru,
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def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$dst, GPR:$base_wb),
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(ins GPR:$base, am2offset:$offset), IndexModeNone,
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LdFrm, IIC_iLoad_ru,
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"ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
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let Inst{21} = 1; // overwrite
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}
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def LDRBT : AI2ldstpo<1, 1, (outs GPR:$dst, GPR:$base_wb),
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(ins GPR:$base,am2offset:$offset), LdFrm, IIC_iLoad_bh_ru,
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def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
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(ins GPR:$base,am2offset:$offset), IndexModeNone,
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LdFrm, IIC_iLoad_bh_ru,
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"ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
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let Inst{21} = 1; // overwrite
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}
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@ -1646,16 +1654,16 @@ def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
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"strd", "\t$src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
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// Indexed stores
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def STR_PRE : AI2ldstpr<0, 0, (outs GPR:$base_wb),
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def STR_PRE : AI2ldstidx<0, 0, 1, (outs GPR:$base_wb),
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(ins GPR:$src, GPR:$base, am2offset:$offset),
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StFrm, IIC_iStore_ru,
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IndexModePre, StFrm, IIC_iStore_ru,
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"str", "\t$src, [$base, $offset]!", "$base = $base_wb",
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[(set GPR:$base_wb,
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(pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
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def STR_POST : AI2ldstpo<0, 0, (outs GPR:$base_wb),
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def STR_POST : AI2ldstidx<0, 0, 0, (outs GPR:$base_wb),
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(ins GPR:$src, GPR:$base,am2offset:$offset),
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StFrm, IIC_iStore_ru,
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IndexModePost, StFrm, IIC_iStore_ru,
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"str", "\t$src, [$base], $offset", "$base = $base_wb",
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[(set GPR:$base_wb,
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(post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
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@ -1674,16 +1682,16 @@ def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
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[(set GPR:$base_wb, (post_truncsti16 GPR:$src,
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GPR:$base, am3offset:$offset))]>;
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def STRB_PRE : AI2ldstpr<0, 1, (outs GPR:$base_wb),
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def STRB_PRE : AI2ldstidx<0, 1, 1, (outs GPR:$base_wb),
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(ins GPR:$src, GPR:$base,am2offset:$offset),
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StFrm, IIC_iStore_bh_ru,
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IndexModePre, StFrm, IIC_iStore_bh_ru,
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"strb", "\t$src, [$base, $offset]!", "$base = $base_wb",
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[(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
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GPR:$base, am2offset:$offset))]>;
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def STRB_POST: AI2ldstpo<0, 1, (outs GPR:$base_wb),
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def STRB_POST: AI2ldstidx<0, 1, 0, (outs GPR:$base_wb),
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(ins GPR:$src, GPR:$base,am2offset:$offset),
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StFrm, IIC_iStore_bh_ru,
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IndexModePost, StFrm, IIC_iStore_bh_ru,
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"strb", "\t$src, [$base], $offset", "$base = $base_wb",
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[(set GPR:$base_wb, (post_truncsti8 GPR:$src,
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GPR:$base, am2offset:$offset))]>;
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@ -1704,17 +1712,17 @@ def STRD_POST: AI3stdpo<(outs GPR:$base_wb),
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// STRT, STRBT, and STRHT are for disassembly only.
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def STRT : AI2ldstpo<0, 0, (outs GPR:$base_wb),
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def STRT : AI2ldstidx<0, 0, 0, (outs GPR:$base_wb),
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(ins GPR:$src, GPR:$base,am2offset:$offset),
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StFrm, IIC_iStore_ru,
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IndexModeNone, StFrm, IIC_iStore_ru,
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"strt", "\t$src, [$base], $offset", "$base = $base_wb",
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[/* For disassembly only; pattern left blank */]> {
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let Inst{21} = 1; // overwrite
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}
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def STRBT : AI2ldstpo<0, 1, (outs GPR:$base_wb),
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def STRBT : AI2ldstidx<0, 1, 0, (outs GPR:$base_wb),
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(ins GPR:$src, GPR:$base,am2offset:$offset),
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StFrm, IIC_iStore_bh_ru,
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IndexModeNone, StFrm, IIC_iStore_bh_ru,
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"strbt", "\t$src, [$base], $offset", "$base = $base_wb",
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[/* For disassembly only; pattern left blank */]> {
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let Inst{21} = 1; // overwrite
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