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Rewrite targets/rules to generate files for just PowerPC or PPC{32,64}

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15862 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman 2004-08-17 05:11:54 +00:00
parent 8283ec7c1c
commit 9e36843964
1 changed files with 18 additions and 19 deletions
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37
lib/Target/PowerPC/Makefile
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@ -13,39 +13,38 @@ include $(LEVEL)/Makefile.common
TARGET = PowerPC TARGET = PowerPC
# Make sure that tblgen is run, first thing. # Make sure that tblgen is run, first thing.
$(SourceDepend): PowerPCGenRegisterInfo.h.inc PowerPCGenRegisterNames.inc \ $(SourceDepend): PowerPCGenInstrNames.inc PowerPCGenRegisterNames.inc \
PowerPCGenRegisterInfo.inc PowerPCGenInstrNames.inc \ PowerPCGenCodeEmitter.inc PowerPCGenAsmWriter.inc \
PowerPCGenInstrInfo.inc PowerPCGenCodeEmitter.inc \ PPC32GenRegisterInfo.h.inc PPC32GenRegisterInfo.inc PPC32GenInstrInfo.inc \
PowerPCGenAsmWriter.inc PPC64GenRegisterInfo.h.inc PPC64GenRegisterInfo.inc PPC64GenInstrInfo.inc
TDFILES = $(SourceDir)/$(TARGET).td $(wildcard $(SourceDir)/*.td) \ TDFILES = $(wildcard $(SourceDir)/*.td) $(SourceDir)/../Target.td
$(SourceDir)/../Target.td
$(TARGET)GenRegisterNames.inc:: $(TDFILES) $(TBLGEN) %GenRegisterNames.inc:: PPC32.td $(TDFILES) $(TBLGEN)
@echo "Building $(TARGET).td register names with tblgen" @echo "Building PowerPC register names with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@ $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
$(TARGET)GenRegisterInfo.h.inc:: $(TDFILES) $(TBLGEN) %GenRegisterInfo.h.inc:: %.td $(TDFILES) $(TBLGEN)
@echo "Building $(TARGET).td register information header with tblgen" @echo "Building `basename $<` register information header with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@ $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@
$(TARGET)GenRegisterInfo.inc:: $(TDFILES) $(TBLGEN) %GenRegisterInfo.inc:: %.td $(TDFILES) $(TBLGEN)
@echo "Building $(TARGET).td register information implementation with tblgen" @echo "Building `basename $<` register information implementation with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@ $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@
$(TARGET)GenInstrNames.inc:: $(TDFILES) $(TBLGEN) $(TARGET)GenInstrNames.inc:: PPC32.td $(TDFILES) $(TBLGEN)
@echo "Building $(TARGET).td instruction names with tblgen" @echo "Building $(TARGET) instruction names with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@ $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
$(TARGET)GenInstrInfo.inc:: $(TDFILES) $(TBLGEN) %GenInstrInfo.inc:: %.td $(TDFILES) $(TBLGEN)
@echo "Building $(TARGET).td instruction information with tblgen" @echo "Building $(TARGET) instruction information with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@ $(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
$(TARGET)GenCodeEmitter.inc:: $(TDFILES) $(TBLGEN) $(TARGET)GenCodeEmitter.inc:: PPC32.td $(TDFILES) $(TBLGEN)
@echo "Building $(TARGET).td code emitter" @echo "Building $(TARGET) code emitter"
$(VERB) $(TBLGEN) -I $(SourceDir) $< -gen-emitter -o $@ $(VERB) $(TBLGEN) -I $(SourceDir) $< -gen-emitter -o $@
$(TARGET)GenAsmWriter.inc:: $(TDFILES) $(TBLGEN) $(TARGET)GenAsmWriter.inc:: PPC32.td $(TDFILES) $(TBLGEN)
@echo "Building $(TARGET).td assembly writer with tblgen" @echo "Building $(TARGET).td assembly writer with tblgen"
$(VERB) $(TBLGEN) -I $(SourceDir) $< -gen-asm-writer -o $@ $(VERB) $(TBLGEN) -I $(SourceDir) $< -gen-asm-writer -o $@