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Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186098 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2013-07-11 16:22:38 +00:00
parent 73480481f4
commit 9e639e8fd9
11 changed files with 26 additions and 26 deletions
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2
include/llvm/CodeGen/LiveInterval.h
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@ -389,7 +389,7 @@ namespace llvm {
void join(LiveInterval &Other,
const int *ValNoAssignments,
const int *RHSValNoAssignments,
SmallVector<VNInfo*, 16> &NewVNInfo,
SmallVectorImpl<VNInfo *> &NewVNInfo,
MachineRegisterInfo *MRI);
/// isInOneLiveRange - Return true if the range specified is entirely in the

4
include/llvm/CodeGen/LiveVariables.h
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@ -157,8 +157,8 @@ private: // Intermediate data structures
void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
SmallVector<unsigned, 4> &Defs);
void UpdatePhysRegDefs(MachineInstr *MI, SmallVector<unsigned, 4> &Defs);
SmallVectorImpl<unsigned> &Defs);
void UpdatePhysRegDefs(MachineInstr *MI, SmallVectorImpl<unsigned> &Defs);
/// FindLastRefOrPartRef - Return the last reference or partial reference of
/// the specified register.

2
lib/Analysis/CostModel.cpp
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@ -81,7 +81,7 @@ CostModelAnalysis::runOnFunction(Function &F) {
return false;
}
static bool isReverseVectorMask(SmallVector<int, 16> &Mask) {
static bool isReverseVectorMask(SmallVectorImpl<int> &Mask) {
for (unsigned i = 0, MaskSize = Mask.size(); i < MaskSize; ++i)
if (Mask[i] > 0 && Mask[i] != (int)(MaskSize - 1 - i))
return false;

2
lib/Analysis/ScalarEvolution.cpp
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@ -1380,7 +1380,7 @@ const SCEV *ScalarEvolution::getAnyExtendExpr(const SCEV *Op,
///
static bool
CollectAddOperandsWithScales(DenseMap<const SCEV *, APInt> &M,
SmallVector<const SCEV *, 8> &NewOps,
SmallVectorImpl<const SCEV *> &NewOps,
APInt &AccumulatedConstant,
const SCEV *const *Ops, size_t NumOperands,
const APInt &Scale,

2
lib/Analysis/ValueTracking.cpp
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@ -1526,7 +1526,7 @@ Value *llvm::isBytewiseValue(Value *V) {
// struct. To is the result struct built so far, new insertvalue instructions
// build on that.
static Value *BuildSubAggregate(Value *From, Value* To, Type *IndexedType,
SmallVector<unsigned, 10> &Idxs,
SmallVectorImpl<unsigned> &Idxs,
unsigned IdxSkip,
Instruction *InsertBefore) {
llvm::StructType *STy = dyn_cast<llvm::StructType>(IndexedType);

10
lib/Bitcode/Reader/BitcodeReader.h
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@ -258,7 +258,7 @@ private:
/// getValueTypePair - Read a value/type pair out of the specified record from
/// slot 'Slot'. Increment Slot past the number of slots used in the record.
/// Return true on failure.
bool getValueTypePair(SmallVector<uint64_t, 64> &Record, unsigned &Slot,
bool getValueTypePair(SmallVectorImpl<uint64_t> &Record, unsigned &Slot,
unsigned InstNum, Value *&ResVal) {
if (Slot == Record.size()) return true;
unsigned ValNo = (unsigned)Record[Slot++];
@ -282,7 +282,7 @@ private:
/// popValue - Read a value out of the specified record from slot 'Slot'.
/// Increment Slot past the number of slots used by the value in the record.
/// Return true if there is an error.
bool popValue(SmallVector<uint64_t, 64> &Record, unsigned &Slot,
bool popValue(SmallVectorImpl<uint64_t> &Record, unsigned &Slot,
unsigned InstNum, Type *Ty, Value *&ResVal) {
if (getValue(Record, Slot, InstNum, Ty, ResVal))
return true;
@ -292,7 +292,7 @@ private:
}
/// getValue -- Like popValue, but does not increment the Slot number.
bool getValue(SmallVector<uint64_t, 64> &Record, unsigned Slot,
bool getValue(SmallVectorImpl<uint64_t> &Record, unsigned Slot,
unsigned InstNum, Type *Ty, Value *&ResVal) {
ResVal = getValue(Record, Slot, InstNum, Ty);
return ResVal == 0;
@ -300,7 +300,7 @@ private:
/// getValue -- Version of getValue that returns ResVal directly,
/// or 0 if there is an error.
Value *getValue(SmallVector<uint64_t, 64> &Record, unsigned Slot,
Value *getValue(SmallVectorImpl<uint64_t> &Record, unsigned Slot,
unsigned InstNum, Type *Ty) {
if (Slot == Record.size()) return 0;
unsigned ValNo = (unsigned)Record[Slot];
@ -311,7 +311,7 @@ private:
}
/// getValueSigned -- Like getValue, but decodes signed VBRs.
Value *getValueSigned(SmallVector<uint64_t, 64> &Record, unsigned Slot,
Value *getValueSigned(SmallVectorImpl<uint64_t> &Record, unsigned Slot,
unsigned InstNum, Type *Ty) {
if (Slot == Record.size()) return 0;
unsigned ValNo = (unsigned)decodeSignRotatedValue(Record[Slot]);

14
lib/Bitcode/Writer/BitcodeWriter.cpp
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@ -614,7 +614,7 @@ static uint64_t GetOptimizationFlags(const Value *V) {
static void WriteMDNode(const MDNode *N,
const ValueEnumerator &VE,
BitstreamWriter &Stream,
SmallVector<uint64_t, 64> &Record) {
SmallVectorImpl<uint64_t> &Record) {
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
if (N->getOperand(i)) {
Record.push_back(VE.getTypeID(N->getOperand(i)->getType()));
@ -701,7 +701,7 @@ static void WriteFunctionLocalMetadata(const Function &F,
BitstreamWriter &Stream) {
bool StartedMetadataBlock = false;
SmallVector<uint64_t, 64> Record;
const SmallVector<const MDNode *, 8> &Vals = VE.getFunctionLocalMDValues();
const SmallVectorImpl<const MDNode *> &Vals = VE.getFunctionLocalMDValues();
for (unsigned i = 0, e = Vals.size(); i != e; ++i)
if (const MDNode *N = Vals[i])
if (N->isFunctionLocal() && N->getFunction() == &F) {
@ -1078,7 +1078,7 @@ static void WriteModuleConstants(const ValueEnumerator &VE,
/// instruction ID, then it is a forward reference, and it also includes the
/// type ID. The value ID that is written is encoded relative to the InstID.
static bool PushValueAndType(const Value *V, unsigned InstID,
SmallVector<unsigned, 64> &Vals,
SmallVectorImpl<unsigned> &Vals,
ValueEnumerator &VE) {
unsigned ValID = VE.getValueID(V);
// Make encoding relative to the InstID.
@ -1093,21 +1093,21 @@ static bool PushValueAndType(const Value *V, unsigned InstID,
/// pushValue - Like PushValueAndType, but where the type of the value is
/// omitted (perhaps it was already encoded in an earlier operand).
static void pushValue(const Value *V, unsigned InstID,
SmallVector<unsigned, 64> &Vals,
SmallVectorImpl<unsigned> &Vals,
ValueEnumerator &VE) {
unsigned ValID = VE.getValueID(V);
Vals.push_back(InstID - ValID);
}
static void pushValue64(const Value *V, unsigned InstID,
SmallVector<uint64_t, 128> &Vals,
SmallVectorImpl<uint64_t> &Vals,
ValueEnumerator &VE) {
uint64_t ValID = VE.getValueID(V);
Vals.push_back(InstID - ValID);
}
static void pushValueSigned(const Value *V, unsigned InstID,
SmallVector<uint64_t, 128> &Vals,
SmallVectorImpl<uint64_t> &Vals,
ValueEnumerator &VE) {
unsigned ValID = VE.getValueID(V);
int64_t diff = ((int32_t)InstID - (int32_t)ValID);
@ -1117,7 +1117,7 @@ static void pushValueSigned(const Value *V, unsigned InstID,
/// WriteInstruction - Emit an instruction to the specified stream.
static void WriteInstruction(const Instruction &I, unsigned InstID,
ValueEnumerator &VE, BitstreamWriter &Stream,
SmallVector<unsigned, 64> &Vals) {
SmallVectorImpl<unsigned> &Vals) {
unsigned Code = 0;
unsigned AbbrevToUse = 0;
VE.setInstructionID(&I);

2
lib/Bitcode/Writer/ValueEnumerator.h
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@ -125,7 +125,7 @@ public:
const ValueList &getValues() const { return Values; }
const ValueList &getMDValues() const { return MDValues; }
const SmallVector<const MDNode *, 8> &getFunctionLocalMDValues() const {
const SmallVectorImpl<const MDNode *> &getFunctionLocalMDValues() const {
return FunctionLocalMDs;
}
const TypeList &getTypes() const { return Types; }

2
lib/CodeGen/LiveInterval.cpp
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@ -415,7 +415,7 @@ void LiveInterval::removeValNo(VNInfo *ValNo) {
void LiveInterval::join(LiveInterval &Other,
const int *LHSValNoAssignments,
const int *RHSValNoAssignments,
SmallVector<VNInfo*, 16> &NewVNInfo,
SmallVectorImpl<VNInfo *> &NewVNInfo,
MachineRegisterInfo *MRI) {
verify();

4
lib/CodeGen/LiveVariables.cpp
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@ -441,7 +441,7 @@ void LiveVariables::HandleRegMask(const MachineOperand &MO) {
}
void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
SmallVector<unsigned, 4> &Defs) {
SmallVectorImpl<unsigned> &Defs) {
// What parts of the register are previously defined?
SmallSet<unsigned, 32> Live;
if (PhysRegDef[Reg] || PhysRegUse[Reg]) {
@ -484,7 +484,7 @@ void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
}
void LiveVariables::UpdatePhysRegDefs(MachineInstr *MI,
SmallVector<unsigned, 4> &Defs) {
SmallVectorImpl<unsigned> &Defs) {
while (!Defs.empty()) {
unsigned Reg = Defs.back();
Defs.pop_back();

8
lib/CodeGen/MachineLICM.cpp
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@ -172,7 +172,7 @@ namespace {
BitVector &PhysRegDefs,
BitVector &PhysRegClobbers,
SmallSet<int, 32> &StoredFIs,
SmallVector<CandidateInfo, 32> &Candidates);
SmallVectorImpl<CandidateInfo> &Candidates);
/// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the
/// current loop.
@ -404,7 +404,7 @@ void MachineLICM::ProcessMI(MachineInstr *MI,
BitVector &PhysRegDefs,
BitVector &PhysRegClobbers,
SmallSet<int, 32> &StoredFIs,
SmallVector<CandidateInfo, 32> &Candidates) {
SmallVectorImpl<CandidateInfo> &Candidates) {
bool RuledOut = false;
bool HasNonInvariantUse = false;
unsigned Def = 0;
@ -1084,7 +1084,7 @@ bool MachineLICM::CanCauseHighRegPressure(DenseMap<unsigned, int> &Cost,
return true;
for (unsigned i = BackTrace.size(); i != 0; --i) {
SmallVector<unsigned, 8> &RP = BackTrace[i-1];
SmallVectorImpl<unsigned> &RP = BackTrace[i-1];
if (RP[RCId] + Cost >= Limit)
return true;
}
@ -1130,7 +1130,7 @@ void MachineLICM::UpdateBackTraceRegPressure(const MachineInstr *MI) {
// Update register pressure of blocks from loop header to current block.
for (unsigned i = 0, e = BackTrace.size(); i != e; ++i) {
SmallVector<unsigned, 8> &RP = BackTrace[i];
SmallVectorImpl<unsigned> &RP = BackTrace[i];
for (DenseMap<unsigned, int>::iterator CI = Cost.begin(), CE = Cost.end();
CI != CE; ++CI) {
unsigned RCId = CI->first;