mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2026-04-21 08:17:40 +00:00
Factor out more code for computing register live-range informationfor
scheduling, and generalize is so that preserves state across scheduling regions. This fixes incorrect live-range information around terminators and labels, which are effective region boundaries. In place of looking for terminators to anchor inter-block dependencies, introduce special entry and exit scheduling units for this purpose. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64254 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman
+312
-211
@@ -94,6 +94,25 @@ namespace {
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/// HazardRec - The hazard recognizer to use.
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ScheduleHazardRecognizer *HazardRec;
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/// Classes - For live regs that are only used in one register class in a
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/// live range, the register class. If the register is not live, the
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/// corresponding value is null. If the register is live but used in
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/// multiple register classes, the corresponding value is -1 casted to a
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/// pointer.
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const TargetRegisterClass *
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Classes[TargetRegisterInfo::FirstVirtualRegister];
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/// RegRegs - Map registers to all their references within a live range.
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std::multimap<unsigned, MachineOperand *> RegRefs;
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/// The index of the most recent kill (proceding bottom-up), or ~0u if
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/// the register is not live.
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unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister];
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/// The index of the most recent complete def (proceding bottom up), or ~0u
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/// if the register is live.
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unsigned DefIndices[TargetRegisterInfo::FirstVirtualRegister];
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public:
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SchedulePostRATDList(MachineFunction &MF,
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const MachineLoopInfo &MLI,
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@@ -107,10 +126,29 @@ namespace {
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delete HazardRec;
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}
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/// StartBlock - Initialize register live-range state for scheduling in
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/// this block.
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///
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void StartBlock(MachineBasicBlock *BB);
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/// Schedule - Schedule the instruction range using list scheduling.
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///
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void Schedule();
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/// Observe - Update liveness information to account for the current
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/// instruction, which will not be scheduled.
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///
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void Observe(MachineInstr *MI);
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/// FinishBlock - Clean up register live-range state.
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///
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void FinishBlock();
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private:
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void PrescanInstruction(MachineInstr *MI);
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void ScanInstruction(MachineInstr *MI, unsigned Count);
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void ReleaseSucc(SUnit *SU, SDep *SuccEdge);
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void ReleaseSuccessors(SUnit *SU);
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void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
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void ListScheduleTopDown();
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bool BreakAntiDependencies();
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@@ -173,6 +211,19 @@ namespace {
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};
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}
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/// isSchedulingBoundary - Test if the given instruction should be
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/// considered a scheduling boundary. This primarily includes labels
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/// and terminators.
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///
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static bool isSchedulingBoundary(const MachineInstr *MI,
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const MachineFunction &MF) {
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// Terminators and labels can't be scheduled around.
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if (MI->getDesc().isTerminator() || MI->isLabel())
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return true;
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return false;
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}
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bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
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DOUT << "PostRAScheduler\n";
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@@ -187,131 +238,51 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
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// Loop over all of the basic blocks
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for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
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MBB != MBBe; ++MBB) {
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// Initialize register live-range state for scheduling in this block.
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Scheduler.StartBlock(MBB);
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// Schedule each sequence of instructions not interrupted by a label
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// or anything else that effectively needs to shut down scheduling.
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MachineBasicBlock::iterator Current = MBB->end(), Top = MBB->begin();
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for (MachineBasicBlock::iterator I = Current; I != Top; ) {
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MachineInstr *MI = --I;
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if (MI->getDesc().isTerminator() || MI->isLabel()) {
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Scheduler.Run(0, MBB, next(I), Current);
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Scheduler.EmitSchedule();
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Current = I;
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MachineBasicBlock::iterator Current = MBB->end();
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for (MachineBasicBlock::iterator I = Current; I != MBB->begin(); ) {
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MachineInstr *MI = prior(I);
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if (isSchedulingBoundary(MI, Fn)) {
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if (I != Current) {
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Scheduler.Run(0, MBB, I, Current);
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Scheduler.EmitSchedule();
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}
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Scheduler.Observe(MI);
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Current = MI;
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}
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I = MI;
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}
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Scheduler.Run(0, MBB, Top, Current);
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Scheduler.Run(0, MBB, MBB->begin(), Current);
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Scheduler.EmitSchedule();
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// Clean up register live-range state.
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Scheduler.FinishBlock();
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}
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return true;
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}
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/// Schedule - Schedule the DAG using list scheduling.
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void SchedulePostRATDList::Schedule() {
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DOUT << "********** List Scheduling **********\n";
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// Build the scheduling graph.
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BuildSchedGraph();
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if (EnableAntiDepBreaking) {
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if (BreakAntiDependencies()) {
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// We made changes. Update the dependency graph.
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// Theoretically we could update the graph in place:
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// When a live range is changed to use a different register, remove
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// the def's anti-dependence *and* output-dependence edges due to
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// that register, and add new anti-dependence and output-dependence
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// edges based on the next live range of the register.
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SUnits.clear();
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BuildSchedGraph();
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}
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}
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AvailableQueue.initNodes(SUnits);
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ListScheduleTopDown();
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AvailableQueue.releaseState();
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}
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/// getInstrOperandRegClass - Return register class of the operand of an
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/// instruction of the specified TargetInstrDesc.
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static const TargetRegisterClass*
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getInstrOperandRegClass(const TargetRegisterInfo *TRI,
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const TargetInstrDesc &II, unsigned Op) {
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if (Op >= II.getNumOperands())
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return NULL;
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if (II.OpInfo[Op].isLookupPtrRegClass())
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return TRI->getPointerRegClass();
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return TRI->getRegClass(II.OpInfo[Op].RegClass);
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}
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/// CriticalPathStep - Return the next SUnit after SU on the bottom-up
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/// critical path.
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static SDep *CriticalPathStep(SUnit *SU) {
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SDep *Next = 0;
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unsigned NextDepth = 0;
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// Find the predecessor edge with the greatest depth.
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for (SUnit::pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
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P != PE; ++P) {
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SUnit *PredSU = P->getSUnit();
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unsigned PredLatency = P->getLatency();
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unsigned PredTotalLatency = PredSU->getDepth() + PredLatency;
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// In the case of a latency tie, prefer an anti-dependency edge over
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// other types of edges.
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if (NextDepth < PredTotalLatency ||
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(NextDepth == PredTotalLatency && P->getKind() == SDep::Anti)) {
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NextDepth = PredTotalLatency;
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Next = &*P;
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}
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}
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return Next;
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}
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/// BreakAntiDependencies - Identifiy anti-dependencies along the critical path
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/// of the ScheduleDAG and break them by renaming registers.
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/// StartBlock - Initialize register live-range state for scheduling in
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/// this block.
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///
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bool SchedulePostRATDList::BreakAntiDependencies() {
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// The code below assumes that there is at least one instruction,
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// so just duck out immediately if the block is empty.
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if (SUnits.empty()) return false;
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void SchedulePostRATDList::StartBlock(MachineBasicBlock *BB) {
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// Call the superclass.
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ScheduleDAGInstrs::StartBlock(BB);
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// Find the node at the bottom of the critical path.
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SUnit *Max = 0;
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for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
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SUnit *SU = &SUnits[i];
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if (!Max || SU->getDepth() + SU->Latency > Max->getDepth() + Max->Latency)
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Max = SU;
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}
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// Clear out the register class data.
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std::fill(Classes, array_endof(Classes),
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static_cast<const TargetRegisterClass *>(0));
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DOUT << "Critical path has total latency "
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<< (Max->getDepth() + Max->Latency) << "\n";
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// Track progress along the critical path through the SUnit graph as we walk
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// the instructions.
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SUnit *CriticalPathSU = Max;
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MachineInstr *CriticalPathMI = CriticalPathSU->getInstr();
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// For live regs that are only used in one register class in a live range,
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// the register class. If the register is not live, the corresponding value
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// is null. If the register is live but used in multiple register classes,
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// the corresponding value is -1 casted to a pointer.
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const TargetRegisterClass *
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Classes[TargetRegisterInfo::FirstVirtualRegister] = {};
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// Map registers to all their references within a live range.
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std::multimap<unsigned, MachineOperand *> RegRefs;
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// The index of the most recent kill (proceding bottom-up), or ~0u if
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// the register is not live.
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unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister];
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// Initialize the indices to indicate that no registers are live.
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std::fill(KillIndices, array_endof(KillIndices), ~0u);
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// The index of the most recent complete def (proceding bottom up), or ~0u if
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// the register is live.
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unsigned DefIndices[TargetRegisterInfo::FirstVirtualRegister];
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std::fill(DefIndices, array_endof(DefIndices), BB->size());
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// Determine the live-out physregs for this block.
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if (BB->back().getDesc().isReturn())
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if (!BB->empty() && BB->back().getDesc().isReturn())
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// In a return block, examine the function live-out regs.
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for (MachineRegisterInfo::liveout_iterator I = MRI.liveout_begin(),
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E = MRI.liveout_end(); I != E; ++I) {
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@@ -368,6 +339,217 @@ bool SchedulePostRATDList::BreakAntiDependencies() {
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DefIndices[AliasReg] = ~0u;
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}
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}
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}
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/// Schedule - Schedule the instruction range using list scheduling.
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///
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void SchedulePostRATDList::Schedule() {
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DOUT << "********** List Scheduling **********\n";
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// Build the scheduling graph.
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BuildSchedGraph();
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if (EnableAntiDepBreaking) {
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if (BreakAntiDependencies()) {
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// We made changes. Update the dependency graph.
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// Theoretically we could update the graph in place:
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// When a live range is changed to use a different register, remove
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// the def's anti-dependence *and* output-dependence edges due to
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// that register, and add new anti-dependence and output-dependence
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// edges based on the next live range of the register.
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SUnits.clear();
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EntrySU = SUnit();
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ExitSU = SUnit();
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BuildSchedGraph();
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}
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}
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AvailableQueue.initNodes(SUnits);
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ListScheduleTopDown();
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AvailableQueue.releaseState();
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}
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/// Observe - Update liveness information to account for the current
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/// instruction, which will not be scheduled.
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///
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void SchedulePostRATDList::Observe(MachineInstr *MI) {
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PrescanInstruction(MI);
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ScanInstruction(MI, 0);
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}
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/// FinishBlock - Clean up register live-range state.
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///
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void SchedulePostRATDList::FinishBlock() {
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RegRefs.clear();
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// Call the superclass.
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ScheduleDAGInstrs::FinishBlock();
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}
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/// getInstrOperandRegClass - Return register class of the operand of an
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/// instruction of the specified TargetInstrDesc.
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static const TargetRegisterClass*
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getInstrOperandRegClass(const TargetRegisterInfo *TRI,
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const TargetInstrDesc &II, unsigned Op) {
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if (Op >= II.getNumOperands())
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return NULL;
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if (II.OpInfo[Op].isLookupPtrRegClass())
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return TRI->getPointerRegClass();
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return TRI->getRegClass(II.OpInfo[Op].RegClass);
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}
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/// CriticalPathStep - Return the next SUnit after SU on the bottom-up
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/// critical path.
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static SDep *CriticalPathStep(SUnit *SU) {
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SDep *Next = 0;
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unsigned NextDepth = 0;
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// Find the predecessor edge with the greatest depth.
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for (SUnit::pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
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P != PE; ++P) {
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SUnit *PredSU = P->getSUnit();
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unsigned PredLatency = P->getLatency();
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unsigned PredTotalLatency = PredSU->getDepth() + PredLatency;
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// In the case of a latency tie, prefer an anti-dependency edge over
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// other types of edges.
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if (NextDepth < PredTotalLatency ||
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(NextDepth == PredTotalLatency && P->getKind() == SDep::Anti)) {
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NextDepth = PredTotalLatency;
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Next = &*P;
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}
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}
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return Next;
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}
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void SchedulePostRATDList::PrescanInstruction(MachineInstr *MI) {
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// Scan the register operands for this instruction and update
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// Classes and RegRefs.
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg()) continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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const TargetRegisterClass *NewRC =
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getInstrOperandRegClass(TRI, MI->getDesc(), i);
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// For now, only allow the register to be changed if its register
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// class is consistent across all uses.
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if (!Classes[Reg] && NewRC)
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Classes[Reg] = NewRC;
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else if (!NewRC || Classes[Reg] != NewRC)
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Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
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// Now check for aliases.
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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// If an alias of the reg is used during the live range, give up.
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// Note that this allows us to skip checking if AntiDepReg
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// overlaps with any of the aliases, among other things.
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unsigned AliasReg = *Alias;
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if (Classes[AliasReg]) {
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Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
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Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
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}
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}
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// If we're still willing to consider this register, note the reference.
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if (Classes[Reg] != reinterpret_cast<TargetRegisterClass *>(-1))
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RegRefs.insert(std::make_pair(Reg, &MO));
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}
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}
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void SchedulePostRATDList::ScanInstruction(MachineInstr *MI,
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unsigned Count) {
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// Update liveness.
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// Proceding upwards, registers that are defed but not used in this
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// instruction are now dead.
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg()) continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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if (!MO.isDef()) continue;
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// Ignore two-addr defs.
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if (MI->isRegReDefinedByTwoAddr(i)) continue;
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DefIndices[Reg] = Count;
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KillIndices[Reg] = ~0u;
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Classes[Reg] = 0;
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RegRefs.erase(Reg);
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// Repeat, for all subregs.
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for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
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*Subreg; ++Subreg) {
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unsigned SubregReg = *Subreg;
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DefIndices[SubregReg] = Count;
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KillIndices[SubregReg] = ~0u;
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Classes[SubregReg] = 0;
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RegRefs.erase(SubregReg);
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}
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// Conservatively mark super-registers as unusable.
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for (const unsigned *Super = TRI->getSuperRegisters(Reg);
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*Super; ++Super) {
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unsigned SuperReg = *Super;
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Classes[SuperReg] = reinterpret_cast<TargetRegisterClass *>(-1);
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}
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}
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg()) continue;
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unsigned Reg = MO.getReg();
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if (Reg == 0) continue;
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if (!MO.isUse()) continue;
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const TargetRegisterClass *NewRC =
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getInstrOperandRegClass(TRI, MI->getDesc(), i);
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// For now, only allow the register to be changed if its register
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// class is consistent across all uses.
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if (!Classes[Reg] && NewRC)
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Classes[Reg] = NewRC;
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else if (!NewRC || Classes[Reg] != NewRC)
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Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
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RegRefs.insert(std::make_pair(Reg, &MO));
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// It wasn't previously live but now it is, this is a kill.
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if (KillIndices[Reg] == ~0u) {
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KillIndices[Reg] = Count;
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DefIndices[Reg] = ~0u;
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}
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// Repeat, for all aliases.
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for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
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unsigned AliasReg = *Alias;
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if (KillIndices[AliasReg] == ~0u) {
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KillIndices[AliasReg] = Count;
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DefIndices[AliasReg] = ~0u;
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}
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}
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}
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}
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/// BreakAntiDependencies - Identifiy anti-dependencies along the critical path
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/// of the ScheduleDAG and break them by renaming registers.
|
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///
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bool SchedulePostRATDList::BreakAntiDependencies() {
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// The code below assumes that there is at least one instruction,
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// so just duck out immediately if the block is empty.
|
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if (SUnits.empty()) return false;
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// Find the node at the bottom of the critical path.
|
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SUnit *Max = 0;
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for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
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SUnit *SU = &SUnits[i];
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if (!Max || SU->getDepth() + SU->Latency > Max->getDepth() + Max->Latency)
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Max = SU;
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}
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DOUT << "Critical path has total latency "
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<< (Max->getDepth() + Max->Latency) << "\n";
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// Track progress along the critical path through the SUnit graph as we walk
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// the instructions.
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SUnit *CriticalPathSU = Max;
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MachineInstr *CriticalPathMI = CriticalPathSU->getInstr();
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// Consider this pattern:
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// A = ...
|
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@@ -481,43 +663,19 @@ bool SchedulePostRATDList::BreakAntiDependencies() {
|
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}
|
||||
}
|
||||
|
||||
// Scan the register operands for this instruction and update
|
||||
// Classes and RegRefs.
|
||||
PrescanInstruction(MI);
|
||||
|
||||
// If this instruction has a use of AntiDepReg, breaking it
|
||||
// is invalid.
|
||||
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
||||
MachineOperand &MO = MI->getOperand(i);
|
||||
if (!MO.isReg()) continue;
|
||||
unsigned Reg = MO.getReg();
|
||||
if (Reg == 0) continue;
|
||||
const TargetRegisterClass *NewRC =
|
||||
getInstrOperandRegClass(TRI, MI->getDesc(), i);
|
||||
|
||||
// If this instruction has a use of AntiDepReg, breaking it
|
||||
// is invalid.
|
||||
if (MO.isUse() && AntiDepReg == Reg)
|
||||
if (MO.isUse() && AntiDepReg == Reg) {
|
||||
AntiDepReg = 0;
|
||||
|
||||
// For now, only allow the register to be changed if its register
|
||||
// class is consistent across all uses.
|
||||
if (!Classes[Reg] && NewRC)
|
||||
Classes[Reg] = NewRC;
|
||||
else if (!NewRC || Classes[Reg] != NewRC)
|
||||
Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
|
||||
|
||||
// Now check for aliases.
|
||||
for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
|
||||
// If an alias of the reg is used during the live range, give up.
|
||||
// Note that this allows us to skip checking if AntiDepReg
|
||||
// overlaps with any of the aliases, among other things.
|
||||
unsigned AliasReg = *Alias;
|
||||
if (Classes[AliasReg]) {
|
||||
Classes[AliasReg] = reinterpret_cast<TargetRegisterClass *>(-1);
|
||||
Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
// If we're still willing to consider this register, note the reference.
|
||||
if (Classes[Reg] != reinterpret_cast<TargetRegisterClass *>(-1))
|
||||
RegRefs.insert(std::make_pair(Reg, &MO));
|
||||
}
|
||||
|
||||
// Determine AntiDepReg's register class, if it is live and is
|
||||
@@ -584,71 +742,7 @@ bool SchedulePostRATDList::BreakAntiDependencies() {
|
||||
}
|
||||
}
|
||||
|
||||
// Update liveness.
|
||||
// Proceding upwards, registers that are defed but not used in this
|
||||
// instruction are now dead.
|
||||
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
||||
MachineOperand &MO = MI->getOperand(i);
|
||||
if (!MO.isReg()) continue;
|
||||
unsigned Reg = MO.getReg();
|
||||
if (Reg == 0) continue;
|
||||
if (!MO.isDef()) continue;
|
||||
// Ignore two-addr defs.
|
||||
if (MI->isRegReDefinedByTwoAddr(i)) continue;
|
||||
|
||||
DefIndices[Reg] = Count;
|
||||
KillIndices[Reg] = ~0u;
|
||||
Classes[Reg] = 0;
|
||||
RegRefs.erase(Reg);
|
||||
// Repeat, for all subregs.
|
||||
for (const unsigned *Subreg = TRI->getSubRegisters(Reg);
|
||||
*Subreg; ++Subreg) {
|
||||
unsigned SubregReg = *Subreg;
|
||||
DefIndices[SubregReg] = Count;
|
||||
KillIndices[SubregReg] = ~0u;
|
||||
Classes[SubregReg] = 0;
|
||||
RegRefs.erase(SubregReg);
|
||||
}
|
||||
// Conservatively mark super-registers as unusable.
|
||||
for (const unsigned *Super = TRI->getSuperRegisters(Reg);
|
||||
*Super; ++Super) {
|
||||
unsigned SuperReg = *Super;
|
||||
Classes[SuperReg] = reinterpret_cast<TargetRegisterClass *>(-1);
|
||||
}
|
||||
}
|
||||
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
|
||||
MachineOperand &MO = MI->getOperand(i);
|
||||
if (!MO.isReg()) continue;
|
||||
unsigned Reg = MO.getReg();
|
||||
if (Reg == 0) continue;
|
||||
if (!MO.isUse()) continue;
|
||||
|
||||
const TargetRegisterClass *NewRC =
|
||||
getInstrOperandRegClass(TRI, MI->getDesc(), i);
|
||||
|
||||
// For now, only allow the register to be changed if its register
|
||||
// class is consistent across all uses.
|
||||
if (!Classes[Reg] && NewRC)
|
||||
Classes[Reg] = NewRC;
|
||||
else if (!NewRC || Classes[Reg] != NewRC)
|
||||
Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
|
||||
|
||||
RegRefs.insert(std::make_pair(Reg, &MO));
|
||||
|
||||
// It wasn't previously live but now it is, this is a kill.
|
||||
if (KillIndices[Reg] == ~0u) {
|
||||
KillIndices[Reg] = Count;
|
||||
DefIndices[Reg] = ~0u;
|
||||
}
|
||||
// Repeat, for all aliases.
|
||||
for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
|
||||
unsigned AliasReg = *Alias;
|
||||
if (KillIndices[AliasReg] == ~0u) {
|
||||
KillIndices[AliasReg] = Count;
|
||||
DefIndices[AliasReg] = ~0u;
|
||||
}
|
||||
}
|
||||
}
|
||||
ScanInstruction(MI, Count);
|
||||
}
|
||||
assert(Count == ~0u && "Count mismatch!");
|
||||
|
||||
@@ -679,9 +773,17 @@ void SchedulePostRATDList::ReleaseSucc(SUnit *SU, SDep *SuccEdge) {
|
||||
// their latencies.
|
||||
SuccSU->setDepthToAtLeast(SU->getDepth() + SuccEdge->getLatency());
|
||||
|
||||
if (SuccSU->NumPredsLeft == 0) {
|
||||
// If all the node's predecessors are scheduled, this node is ready
|
||||
// to be scheduled. Ignore the special ExitSU node.
|
||||
if (SuccSU->NumPredsLeft == 0 && SuccSU != &ExitSU)
|
||||
PendingQueue.push_back(SuccSU);
|
||||
}
|
||||
}
|
||||
|
||||
/// ReleaseSuccessors - Call ReleaseSucc on each of SU's successors.
|
||||
void SchedulePostRATDList::ReleaseSuccessors(SUnit *SU) {
|
||||
for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
|
||||
I != E; ++I)
|
||||
ReleaseSucc(SU, &*I);
|
||||
}
|
||||
|
||||
/// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending
|
||||
@@ -695,11 +797,7 @@ void SchedulePostRATDList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
|
||||
assert(CurCycle >= SU->getDepth() && "Node scheduled above its depth!");
|
||||
SU->setDepthToAtLeast(CurCycle);
|
||||
|
||||
// Top down: release successors.
|
||||
for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
|
||||
I != E; ++I)
|
||||
ReleaseSucc(SU, &*I);
|
||||
|
||||
ReleaseSuccessors(SU);
|
||||
SU->isScheduled = true;
|
||||
AvailableQueue.ScheduledNode(SU);
|
||||
}
|
||||
@@ -709,6 +807,9 @@ void SchedulePostRATDList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
|
||||
void SchedulePostRATDList::ListScheduleTopDown() {
|
||||
unsigned CurCycle = 0;
|
||||
|
||||
// Release any successors of the special Entry node.
|
||||
ReleaseSuccessors(&EntrySU);
|
||||
|
||||
// All leaves to Available queue.
|
||||
for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
|
||||
// It is available if it has no predecessors.
|
||||
@@ -717,7 +818,7 @@ void SchedulePostRATDList::ListScheduleTopDown() {
|
||||
SUnits[i].isAvailable = true;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// While Available queue is not empty, grab the node with the highest
|
||||
// priority. If it is not ready put it back. Schedule the node.
|
||||
std::vector<SUnit*> NotReady;
|
||||
|
||||
Reference in New Issue
Block a user