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Add instruction encodings / disassembly support for l6r instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173288 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne 2013-01-23 20:08:11 +00:00
parent b09350d9a5
commit 9e6a5a3746
4 changed files with 39 additions and 6 deletions
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25
lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
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@ -170,6 +170,11 @@ static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst,
uint64_t Address, uint64_t Address,
const void *Decoder); const void *Decoder);
static DecodeStatus DecodeL6RInstruction(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
#include "XCoreGenDisassemblerTables.inc" #include "XCoreGenDisassemblerTables.inc"
static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
@ -572,6 +577,26 @@ DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
return S; return S;
} }
static DecodeStatus
DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2, Op3, Op4, Op5, Op6;
DecodeStatus S =
Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
if (S != MCDisassembler::Success)
return S;
S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6);
if (S != MCDisassembler::Success)
return S;
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder);
return S;
}
MCDisassembler::DecodeStatus MCDisassembler::DecodeStatus
XCoreDisassembler::getInstruction(MCInst &instr, XCoreDisassembler::getInstruction(MCInst &instr,
uint64_t &Size, uint64_t &Size,

6
lib/Target/XCore/XCoreInstrFormats.td
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@ -226,6 +226,10 @@ class _L5R<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<4, outs, ins, asmstr, pattern> { : InstXCore<4, outs, ins, asmstr, pattern> {
} }
class _L6R<dag outs, dag ins, string asmstr, list<dag> pattern> class _FL6R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<4, outs, ins, asmstr, pattern> { : InstXCore<4, outs, ins, asmstr, pattern> {
let Inst{31-27} = opc;
let Inst{15-11} = 0b11111;
let DecoderMethod = "DecodeL6RInstruction";
} }

9
lib/Target/XCore/XCoreInstrInfo.td
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@ -502,11 +502,10 @@ def LDIV_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
// Six operand long // Six operand long
def LMUL_l6r : _L6R<(outs GRRegs:$dst1, GRRegs:$dst2), def LMUL_l6r : _FL6R<
(ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, 0b00000, (outs GRRegs:$dst1, GRRegs:$dst2),
GRRegs:$src4), (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, GRRegs:$src4),
"lmul $dst1, $dst2, $src1, $src2, $src3, $src4", "lmul $dst1, $dst2, $src1, $src2, $src3, $src4", []>;
[]>;
// Register - U6 // Register - U6

5
test/MC/Disassembler/XCore/xcore.txt
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@ -456,3 +456,8 @@
# CHECK: bl 38631 # CHECK: bl 38631
0x25 0xf0 0xe7 0xd2 0x25 0xf0 0xe7 0xd2
# l6r instructions
# CHECK: lmul r11, r0, r2, r5, r8, r10
0xf9 0xfa 0x02 0x06