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https://github.com/c64scene-ar/llvm-6502.git
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Add instruction encodings / disassembly support for l6r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173288 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -170,6 +170,11 @@ static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeL6RInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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#include "XCoreGenDisassemblerTables.inc"
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static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
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@ -572,6 +577,26 @@ DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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return S;
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}
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static DecodeStatus
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DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Op1, Op2, Op3, Op4, Op5, Op6;
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DecodeStatus S =
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Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
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if (S != MCDisassembler::Success)
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return S;
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S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6);
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if (S != MCDisassembler::Success)
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return S;
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder);
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return S;
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}
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MCDisassembler::DecodeStatus
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XCoreDisassembler::getInstruction(MCInst &instr,
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uint64_t &Size,
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@ -226,6 +226,10 @@ class _L5R<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<4, outs, ins, asmstr, pattern> {
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}
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class _L6R<dag outs, dag ins, string asmstr, list<dag> pattern>
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class _FL6R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<4, outs, ins, asmstr, pattern> {
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let Inst{31-27} = opc;
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let Inst{15-11} = 0b11111;
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let DecoderMethod = "DecodeL6RInstruction";
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}
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@ -502,11 +502,10 @@ def LDIV_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
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// Six operand long
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def LMUL_l6r : _L6R<(outs GRRegs:$dst1, GRRegs:$dst2),
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(ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3,
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GRRegs:$src4),
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"lmul $dst1, $dst2, $src1, $src2, $src3, $src4",
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[]>;
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def LMUL_l6r : _FL6R<
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0b00000, (outs GRRegs:$dst1, GRRegs:$dst2),
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(ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, GRRegs:$src4),
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"lmul $dst1, $dst2, $src1, $src2, $src3, $src4", []>;
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// Register - U6
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@ -456,3 +456,8 @@
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# CHECK: bl 38631
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0x25 0xf0 0xe7 0xd2
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# l6r instructions
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# CHECK: lmul r11, r0, r2, r5, r8, r10
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0xf9 0xfa 0x02 0x06
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