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Clarify naming and correct conditional so that CMP and CMN instructions get the Rn operand encoded properly

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57252 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2008-10-07 17:42:09 +00:00
parent 17a415a4f2
commit 9e729a2de5
1 changed files with 5 additions and 8 deletions
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13
lib/Target/ARM/ARMCodeEmitter.cpp
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@@ -392,14 +392,11 @@ unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI,
// Encode first non-shifter register operand if there is one. // Encode first non-shifter register operand if there is one.
unsigned Format = TID.TSFlags & ARMII::FormMask; unsigned Format = TID.TSFlags & ARMII::FormMask;
bool isUnary = (Format == ARMII::DPRdMisc || bool hasRnOperand= !(Format == ARMII::DPRdMisc ||
Format == ARMII::DPRdIm || Format == ARMII::DPRdIm ||
Format == ARMII::DPRdReg || Format == ARMII::DPRdReg ||
Format == ARMII::DPRdSoReg || Format == ARMII::DPRdSoReg);
Format == ARMII::DPRnIm || if (hasRnOperand) {
Format == ARMII::DPRnReg ||
Format == ARMII::DPRnSoReg);
if (!isUnary) {
Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift; Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
++OpIdx; ++OpIdx;
} }