From 9e76fea3abd4229749e6ead46a0016cabff4a056 Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Thu, 20 Nov 2008 03:11:19 +0000 Subject: [PATCH] Remove the "fast" form of the list-burr scheduler, and use the dedicated "fast" scheduler in -fast mode instead, which is faster. This speeds up llc -fast by a few percent on some testcases -- the speedup only happens for code not handled by fast-isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59700 91177308-0d34-0410-b5e6-96231b3b80d8 --- .../SelectionDAG/ScheduleDAGRRList.cpp | 77 +++---------------- lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 12 +-- 2 files changed, 15 insertions(+), 74 deletions(-) diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index 98048dfd5d4..a143d351501 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -59,10 +59,6 @@ private: /// it is top-down. bool isBottomUp; - /// Fast - True if we are performing fast scheduling. - /// - bool Fast; - /// AvailableQueue - The priority queue to use for the available SUnits. SchedulingPriorityQueue *AvailableQueue; @@ -75,9 +71,9 @@ private: public: ScheduleDAGRRList(SelectionDAG *dag, MachineBasicBlock *bb, - const TargetMachine &tm, bool isbottomup, bool f, + const TargetMachine &tm, bool isbottomup, SchedulingPriorityQueue *availqueue) - : ScheduleDAGSDNodes(dag, bb, tm), isBottomUp(isbottomup), Fast(f), + : ScheduleDAGSDNodes(dag, bb, tm), isBottomUp(isbottomup), AvailableQueue(availqueue) { } @@ -187,10 +183,8 @@ void ScheduleDAGRRList::Schedule() { DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su) SUnits[su].dumpAll(this)); - if (!Fast) { - CalculateDepths(); - CalculateHeights(); - } + CalculateDepths(); + CalculateHeights(); InitDAGTopologicalSorting(); AvailableQueue->initNodes(SUnits); @@ -203,8 +197,7 @@ void ScheduleDAGRRList::Schedule() { AvailableQueue->releaseState(); - if (!Fast) - CommuteNodesToReducePressure(); + CommuteNodesToReducePressure(); } /// CommuteNodesToReducePressure - If a node is two-address and commutable, and @@ -1431,48 +1424,6 @@ namespace { }; - class VISIBILITY_HIDDEN BURegReductionFastPriorityQueue - : public RegReductionPriorityQueue { - // SethiUllmanNumbers - The SethiUllman number for each node. - std::vector SethiUllmanNumbers; - - public: - BURegReductionFastPriorityQueue(const TargetInstrInfo *tii, - const TargetRegisterInfo *tri) - : RegReductionPriorityQueue(tii, tri) {} - - void initNodes(std::vector &sunits) { - RegReductionPriorityQueue::initNodes(sunits); - // Calculate node priorities. - CalculateSethiUllmanNumbers(); - } - - void addNode(const SUnit *SU) { - unsigned SUSize = SethiUllmanNumbers.size(); - if (SUnits->size() > SUSize) - SethiUllmanNumbers.resize(SUSize*2, 0); - CalcNodeBUSethiUllmanNumber(SU, SethiUllmanNumbers); - } - - void updateNode(const SUnit *SU) { - SethiUllmanNumbers[SU->NodeNum] = 0; - CalcNodeBUSethiUllmanNumber(SU, SethiUllmanNumbers); - } - - void releaseState() { - RegReductionPriorityQueue::releaseState(); - SethiUllmanNumbers.clear(); - } - - unsigned getNodePriority(const SUnit *SU) const { - return SethiUllmanNumbers[SU->NodeNum]; - } - - private: - void CalculateSethiUllmanNumbers(); - }; - - class VISIBILITY_HIDDEN TDRegReductionPriorityQueue : public RegReductionPriorityQueue { // SethiUllmanNumbers - The SethiUllman number for each node. @@ -1756,12 +1707,6 @@ void BURegReductionPriorityQueue::CalculateSethiUllmanNumbers() { for (unsigned i = 0, e = SUnits->size(); i != e; ++i) CalcNodeBUSethiUllmanNumber(&(*SUnits)[i], SethiUllmanNumbers); } -void BURegReductionFastPriorityQueue::CalculateSethiUllmanNumbers() { - SethiUllmanNumbers.assign(SUnits->size(), 0); - - for (unsigned i = 0, e = SUnits->size(); i != e; ++i) - CalcNodeBUSethiUllmanNumber(&(*SUnits)[i], SethiUllmanNumbers); -} /// LimitedSumOfUnscheduledPredsOfSuccs - Compute the sum of the unscheduled /// predecessors of the successors of the SUnit SU. Stop when the provided @@ -1843,18 +1788,14 @@ llvm::ScheduleDAG* llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, SelectionDAG *DAG, const TargetMachine *TM, MachineBasicBlock *BB, - bool Fast) { + bool) { const TargetInstrInfo *TII = TM->getInstrInfo(); const TargetRegisterInfo *TRI = TM->getRegisterInfo(); - if (Fast) - return new ScheduleDAGRRList(DAG, BB, *TM, true, true, - new BURegReductionFastPriorityQueue(TII, TRI)); - BURegReductionPriorityQueue *PQ = new BURegReductionPriorityQueue(TII, TRI); ScheduleDAGRRList *SD = - new ScheduleDAGRRList(DAG, BB, *TM, true, false, PQ); + new ScheduleDAGRRList(DAG, BB, *TM, true, PQ); PQ->setScheduleDAG(SD); return SD; } @@ -1863,13 +1804,13 @@ llvm::ScheduleDAG* llvm::createTDRRListDAGScheduler(SelectionDAGISel *IS, SelectionDAG *DAG, const TargetMachine *TM, MachineBasicBlock *BB, - bool Fast) { + bool) { const TargetInstrInfo *TII = TM->getInstrInfo(); const TargetRegisterInfo *TRI = TM->getRegisterInfo(); TDRegReductionPriorityQueue *PQ = new TDRegReductionPriorityQueue(TII, TRI); - ScheduleDAGRRList *SD = new ScheduleDAGRRList(DAG, BB, *TM, false, Fast, PQ); + ScheduleDAGRRList *SD = new ScheduleDAGRRList(DAG, BB, *TM, false, PQ); PQ->setScheduleDAG(SD); return SD; } diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index e43b32535c3..079e95f25b0 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -138,13 +138,13 @@ namespace llvm { bool Fast) { TargetLowering &TLI = IS->getTargetLowering(); - if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) { + if (Fast) + return createFastDAGScheduler(IS, DAG, TM, BB, Fast); + if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) return createTDListDAGScheduler(IS, DAG, TM, BB, Fast); - } else { - assert(TLI.getSchedulingPreference() == - TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); - return createBURRListDAGScheduler(IS, DAG, TM, BB, Fast); - } + assert(TLI.getSchedulingPreference() == + TargetLowering::SchedulingForRegPressure && "Unknown sched type!"); + return createBURRListDAGScheduler(IS, DAG, TM, BB, Fast); } }