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synced 2024-08-21 18:29:46 +00:00
Enable load / store multiple pass for Thumb2. It's not using ldrd / strd yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78104 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -615,12 +615,15 @@ bool ARMLoadStoreOpt::MergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
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return false;
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bool isDPR = NewOpc == ARM::FLDMD || NewOpc == ARM::FSTMD;
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unsigned Offset = isAM5
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? ARM_AM::getAM5Opc((AddSub == ARM_AM::sub) ? ARM_AM::db : ARM_AM::ia,
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true, isDPR ? 2 : 1)
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: (isAM2
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? ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift)
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: Bytes);
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unsigned Offset = 0;
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if (isAM5)
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Offset = ARM_AM::getAM5Opc((AddSub == ARM_AM::sub)
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? ARM_AM::db
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: ARM_AM::ia, true, (isDPR ? 2 : 1));
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else if (isAM2)
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Offset = ARM_AM::getAM2Opc(AddSub, Bytes, ARM_AM::no_shift);
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else
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Offset = AddSub == ARM_AM::sub ? -Bytes : Bytes;
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if (isLd) {
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if (isAM5)
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// FLDMS, FLDMD
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@ -101,8 +101,9 @@ bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM,
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bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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// FIXME: temporarily disabling load / store optimization pass for Thumb mode.
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if (OptLevel != CodeGenOpt::None && !DisableLdStOpti && !Subtarget.isThumb())
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// FIXME: temporarily disabling load / store optimization pass for Thumb1 mode.
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if (OptLevel != CodeGenOpt::None && !DisableLdStOpti &&
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!Subtarget.isThumb1Only())
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PM.add(createARMLoadStoreOptimizationPass());
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if (OptLevel != CodeGenOpt::None &&
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@ -599,6 +599,7 @@ void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
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// FIXME
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bool isLDM = (MI->getOpcode() == ARM::LDM ||
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MI->getOpcode() == ARM::LDM_RET ||
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MI->getOpcode() == ARM::t2LDM ||
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MI->getOpcode() == ARM::t2LDM_RET);
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O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
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} else
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40
test/CodeGen/Thumb2/thumb2-ldm.ll
Normal file
40
test/CodeGen/Thumb2/thumb2-ldm.ll
Normal file
@ -0,0 +1,40 @@
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; RUN: llvm-as < %s | llc -march=thumb -mattr=+thumb2 | FileCheck %s
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@X = external global [0 x i32] ; <[0 x i32]*> [#uses=5]
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define i32 @t1() {
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; CHECK: t1:
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; CHECK: stmfd sp!, {r7, lr}
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; CHECK: ldmfd sp!, {r7, pc}
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%tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 0) ; <i32> [#uses=1]
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%tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1) ; <i32> [#uses=1]
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%tmp4 = tail call i32 @f1( i32 %tmp, i32 %tmp3 ) ; <i32> [#uses=1]
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ret i32 %tmp4
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}
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define i32 @t2() {
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; CHECK: t2:
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; CHECK: stmfd sp!, {r7, lr}
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; CHECK: ldmia
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; CHECK: ldmfd sp!, {r7, pc}
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%tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; <i32> [#uses=1]
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%tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; <i32> [#uses=1]
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%tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 4) ; <i32> [#uses=1]
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%tmp6 = tail call i32 @f2( i32 %tmp, i32 %tmp3, i32 %tmp5 ) ; <i32> [#uses=1]
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ret i32 %tmp6
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}
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define i32 @t3() {
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; CHECK: t3:
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; CHECK: stmfd sp!, {r7, lr}
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; CHECK: ldmfd sp!, {r7, pc}
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%tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1) ; <i32> [#uses=1]
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%tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; <i32> [#uses=1]
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%tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; <i32> [#uses=1]
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%tmp6 = tail call i32 @f2( i32 %tmp, i32 %tmp3, i32 %tmp5 ) ; <i32> [#uses=1]
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ret i32 %tmp6
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}
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declare i32 @f1(i32, i32)
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declare i32 @f2(i32, i32, i32)
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